Commits · dc8d765c669c35b0d396b5afe5085c08686f7330 · Projects / Platform-independent core collection · GitLab

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May 03, 2024
- Add gc_argb_led_drv · 67d71a85
  Tristan Gingold authored 1 year ago
  
  67d71a85
Jan 16, 2024
- Add a testbench for generic_async_fifo_mixedw · 9ef6f829
  Tristan Gingold authored 1 year ago
  
  9ef6f829
Dec 06, 2023
- Addition of the generated file wb_uart_regs.vh and changes in the comments of... · 87660e4c
  Konstantinos Blantos authored 1 year ago
```
Addition of the generated file wb_uart_regs.vh and changes in the comments of the new registers for PHYSICAL/VIRTUAL UART
```
  87660e4c
May 10, 2023
- testbench: fix gc_cordic testbench · 01d716ae
  Dimitris Lampridis authored 1 year ago
  
  01d716ae
May 08, 2023
- Single-file cordic fixing most of the quirks of the previous implementation with testbench. · c00a45b0
  Nathan Pittet authored 2 years ago and Dimitris Lampridis committed 1 year ago
  
  c00a45b0
- dsp/gc_cordic: move testbench to use Logger/UnitTest code · 4ca7b6ce
  Tomasz Wlostowski authored 2 years ago and Dimitris Lampridis committed 1 year ago
  
  4ca7b6ce
- dsp: testbench for gc_pipelined_fir_filter · 389c160a
  Tomasz Wlostowski authored 3 years ago and Dimitris Lampridis committed 1 year ago
  
  389c160a
- dsp: testbench for gc_cordic · cde0b2a0
  Tomasz Wlostowski authored 3 years ago and Dimitris Lampridis committed 1 year ago
  
  cde0b2a0
May 05, 2023
- testbench: add wb_uart_regs.vh · cb30e89d
  Tristan Gingold authored 1 year ago
  
  cb30e89d
May 02, 2023
- wb_fine_pulse_gen: support for configurable pulse width. INTERFACE CHANGED. · f3f17650
  Tomasz Wlostowski authored 3 years ago and Tristan Gingold committed 1 year ago
```
Affected modules (as far as I know): eRTM14/15 and sis83k.
```
  f3f17650
- wb_uart: temporary fix for eRTM UART FIFO issue causing RX data loss. VUART... · 77519447
  Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 1 year ago
```
wb_uart: temporary fix for eRTM UART FIFO issue causing RX data loss. VUART likely not working. FIX BEFORE MERGING!
```
  77519447
Apr 18, 2023
- Add wb_spi_tb form #35 · 9b239051
  Tristan Gingold authored 1 year ago
  
  9b239051
Jan 16, 2023
- Fixed common error in run.sh scripts for axi/ · 631c62f8
  Konstantinos Blantos authored 2 years ago
  
  631c62f8
- Correct License added. Fixes done in order to solve the issue with... · c4c5418c
  Konstantinos Blantos authored 2 years ago
```
Correct License added. Fixes done in order to solve the issue with axi4lite_axi4full_bridge assertion. sim_top_ps_gpio now not run forever
```
  c4c5418c
- update testbench README · 619b35ff
  Dimitris Lampridis authored 2 years ago
  
  619b35ff
- cleanup testbench Makefile · 6c3a2e72
  Dimitris Lampridis authored 2 years ago
  
  6c3a2e72
- Properly ignore auto-generated files in AXI testbenches · 7f284c33
  Dimitris Lampridis authored 2 years ago
  
  7f284c33
- Introduce OSVVM dependency as submodule · 5bc55a5a
  Dimitris Lampridis authored 2 years ago
  
  5bc55a5a
Jan 13, 2023
- Added: Makefile to run automatically all the AXI tests and README file for explanations · ddb03954
  Konstantinos Blantos authored 2 years ago
  
  ddb03954
- Adding Testbench for AXI cores · 7dd450ae
  Konstantinos Blantos authored 2 years ago
  
  7dd450ae
Jun 28, 2022
- radtol: improve secdec_32b package and tb · 21cd321f
  Tristan Gingold authored 2 years ago
  
  21cd321f
- radtol: more fixes · 3f5fa5e9
  Tristan Gingold authored 3 years ago
  
  3f5fa5e9
- radtol: improve secded_32b testbench · 9d62248e
  Tristan Gingold authored 3 years ago
  
  9d62248e
- radtol/secded: add a testbench for secded_32b_pkg · 6df8f915
  Tristan Gingold authored 3 years ago
  
  6df8f915
- tb_secded_ecc.vhd: improve the test · 3f0d47a0
  Tristan Gingold authored 3 years ago
  
  3f0d47a0
- radtol: add a small testbench for secded_ecc.vhd · 7d72ae31
  Tristan Gingold authored 3 years ago
  
  7d72ae31
Sep 30, 2020
- testbench: add a test for gc_ds182x_readout · 2d716057
  Tristan Gingold authored 4 years ago
  
  2d716057
Sep 14, 2020
- wishbone: UART now supports configurable FIFOs · b34b5008
  Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 4 years ago
  
  b34b5008
Sep 09, 2020
- wb_fine_pulse_gen: simplify clock crossings · 101aff2a
  Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 4 years ago
```
Conflicts:
	modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
```
  101aff2a
- xwb_fine_pulse_gen: support for fine delay (ODELAYE3) on Kintex Ultrascale · f3f8dd3d
  Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 4 years ago
  
  f3f8dd3d
- wb_fine_pulse_gen: use double clock rate on Kintex7 Ultrascale, allowing for 1ns resolution · d69bd493
  Tomasz Wlostowski authored 4 years ago and Tristan Gingold committed 4 years ago
  
  d69bd493
- wishbone: added Fine Pulse Generator module · bf538f6e
  Tomasz Wlostowski authored 5 years ago and Tristan Gingold committed 4 years ago
  
  bf538f6e
Sep 03, 2020
- testbench: add a simple test for wb_spi · 0d76517c
  Tristan Gingold authored 4 years ago
  
  0d76517c
Apr 21, 2020
- Move sim/gc_sync_word_wr to testbench/wishbone. · 9f7ee4a5
  Tristan Gingold authored 4 years ago
  
  9f7ee4a5
Apr 20, 2020
- Add a testbench for xwb_indirect. · 85a3419e
  Tristan Gingold authored 4 years ago
  
  85a3419e
Mar 04, 2020
- Add wb16_to_wb32 module. · 6d382629
  Tristan Gingold authored 5 years ago
  
  6d382629
Sep 09, 2019
- Clean-up non-ASCII characters and fix line feeds and terminations in all affected files · fa8df2bb
  Dimitris Lampridis authored 5 years ago
  
  fa8df2bb
Apr 29, 2019
- adding simple testbench for z7_axi_gpio_expander · 350f2b58
  Grzegorz Daniluk authored 5 years ago
  
  350f2b58
Jan 23, 2018
- modules/common: introduced gc_comparator and accompanying testbench · c3cfcfdd
  Dimitris Lampridis authored 7 years ago
  
  c3cfcfdd
Oct 11, 2017
- wishbone/wb_gpio_port: add simple testbench · ec002a60
  Dimitris Lampridis authored 7 years ago
  
  ec002a60