- Mar 05, 2013
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Wesley W. Terpstra authored
In the past we used a generic to set the initial memory contents on altera. Unfortunately, quartus compiles big generics slowly (read: hours). Now we can load from a .mif file instead, which is much faster (seconds). Thus, this old option is no longer needed.
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- Feb 26, 2013
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Wesley W. Terpstra authored
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- Feb 25, 2013
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Wesley W. Terpstra authored
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- Feb 13, 2013
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Wesley W. Terpstra authored
According to Peter Jansweijer, Precision and Questasim had trouble synthesizing the crossbar HDL. After tracking the problem down via email, it appears that these tools cannot handle nested functions correctly; they crash or fail when trying to access the parameters of the lexically enclosing function. Therefore, this patch just outright removes all nested functions.
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- Aug 03, 2012
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Wesley W. Terpstra authored
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- Aug 01, 2012
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Wesley W. Terpstra authored
Each clock domain needs a separate reset line. However, one cannot reset only a single domain---that could cause inconsistency at clock crossing boundaries. This change splits reset lines per clock domain and centralizes generation.
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Wesley W. Terpstra authored
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- May 18, 2012
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
to ensure stabilization.
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Wesley W. Terpstra authored
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- May 14, 2012
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Wesley W. Terpstra authored
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- Mar 28, 2012
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Tomasz Wlostowski authored
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Added: - asynchronous SRAM bus -> Wishbone bridge (wb_async_bridge) - Conmax interconnect (wb_conmax) - GPIO port (wb_gpio_port) - Very simple timer (wb_simple timer) - Simple UART (wb_uart) - Vectored Interrupt controller (wb_vic) - Virtual UART (mmapped FIFO, wb_virtual_uart) - wbgen2 core generator libraries (wbgen2)
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- Mar 13, 2012
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Wesley W. Terpstra authored
Quartus will not process a 'file_open' call during synthesis, so we can instead initialize the RAM with a vhdl constant.
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- Mar 12, 2012
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
Updated uses of the wishbone_pkg to use Tom's naming conventions. Added Manifests for the new files.
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- Mar 07, 2012
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Wesley W. Terpstra authored
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- Mar 06, 2012
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Wesley W. Terpstra authored
manual -- configure bus_end directly layout -- configure bus_end from nested bus layout ... and fix a bug where the dpram size was incorrect
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
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- Mar 05, 2012
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Wesley W. Terpstra authored
record count is 16 bit index aliased decription (to avoid overflow) Added feature: make it easy to relocate a device to a new address Checks added: confirm address ranges to not overlap during synthesis check wbd_begin/end addresses for compatability with the crossbar
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Wesley W. Terpstra authored
Decode the SDWB blocks to create bus addresses in the sdwb_crossbar. I still need to add assertions to confirm the user didn't give bad inputs.
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- Mar 02, 2012
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Wesley W. Terpstra authored
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- Jan 16, 2012
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Tomasz Wlostowski authored
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- Oct 05, 2011
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Tomasz Wlostowski authored
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- Sep 23, 2011
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Tomasz Wlostowski authored
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- Jul 12, 2011
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- Jun 10, 2011
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Tomasz Wlostowski authored
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- Jun 07, 2011
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Tomasz Wlostowski authored
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