When trying to compile for nanoXplore synthesis fails, complaining
about those signals -- although they're unused.

Although not mentioned in section 5.2 of Wishbone B4 specification, when interfacing a pipelined
master to a standard slave, it is also necessary to make sure that if the slave asserts ACK/ERR/RTY
for more than one clock cycle (which a standard slave could do since, according to Rule 3.50 of
Wishbone B4, "the slave deasserts ACK/ERR/RTY in response to the negation of STB"), the master will
still only see a one cycle wide pulse.

wb_reg_link: add generics for instantiating wb adapters, since wb_reg_link works correctly only when used with pipelined wb interfaces

xwb_register_link: also register the CYC signal, otherwise STB remains active for one more cycle after CYC is dropped, which is not compliant with Wishbone

this is needed for VXS integration in which hdlmake is used to generate
a list of files used, these failes are alter copied to a Visual Elite
based project

Apologies for the double renaming, but it occured to me that the constant names were too generic and could cause conflicts.

This is introduced to better match the OHWR VHDL coding style [1].

Old names are preserved for backward compatibility.

[1]: https://www.ohwr.org/projects/vhdl-style

For the few peripherals where it was being used (eg. uart, spi, etc) the output port
has been renamed to "int_o".

The only peripheral that was not touched is "wb_eic.vhd", because this one is being used
by wbgen, and it would require users to update their wbgen tool as well. So, until a new
tool is introduced, wbgen-generated interrupt controllers will have an output port called
wb_int_o".