wb_irq_slave: added clear and enable registers

Include automatic crossbar layout and timing improvement clock cutter.

This makes it possible to connect a slave to the crossbar which is optimized
away by the synthesis tool. This is useful when some slaves attached to the
crossbar are optional.

	removed auto id from irqm_core
        TODO: fix auto IDs for wb_irq_master

Changes to the TCL scripts were needed.
To simplify future changes, the work was handed off to a shared function.

Replaced by a function taking the number of bits in parameter and returning a vector.

c_status_time was one cycle longer than it should be!
this led to the arria5 requiring g_dummy_time-1 in c_vstatus_data
==> after fixing: must increase g_input_to_output_cycles on arria5

there was also a wrong calculation for s_wip with single-lane mode
it was working also by luck because WEL and WIP are usually set
together and are side-by-side, thus masking the c_status_time bug.

For whatever reason, some flash chips don't have the correct number
of dummy cycles in their non-volatile flash by default. This patch
forces these devices to the generic-specified value.