Commits · 75d51c0b92015b48b176374f9a387b2d25fa8198 · Projects / Platform-independent core collection

Dec 13, 2019
- [common] add VHDL functions to upper/lower case characters and strings · 75d51c0b
  Dimitris Lampridis authored 5 years ago
  
  75d51c0b
Oct 21, 2019
- init changelog for first release · be61ce73
  Dimitris Lampridis authored 5 years ago
  
  v1.0.0
  
  be61ce73
Oct 14, 2019
- sw: add SPDX information · 4f414ece
  Federico Vaga authored 5 years ago
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  4f414ece
- sw: add modules_install target on Makefiles · 5ba6c68d
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  5ba6c68d
Oct 08, 2019
- sw: align Makefiles · 7b03c14c
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  7b03c14c
- import htvic 1.3.0 · 0b27a3f7
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  0b27a3f7
Sep 27, 2019
- sw: include header files · 62f22c5f
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  62f22c5f
- sw:i2c: unselecting is superfluous · eea86f41
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  eea86f41
Sep 19, 2019
- sw:drv:spi: fix pending test · f90e7c1d
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f90e7c1d
Sep 11, 2019
- sw: improve build system · 96728bc0
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  96728bc0
Sep 10, 2019
- sw:drv: add SPI driver for spi-ocores · 5d1a20d3
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  5d1a20d3
- sw:drv:i2c: fix directory name · 44fcfbb5
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  44fcfbb5
- sw:drv: add I2C driver from Linux · 58c20ccd
  Federico Vaga authored 5 years ago
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  58c20ccd
Sep 09, 2019
- Clean-up non-ASCII characters and fix line feeds and terminations in all affected files · fa8df2bb
  Dimitris Lampridis authored 5 years ago
  
  fa8df2bb
Aug 07, 2019
- [hdl] allow general-cores modules to work with hdlmake even when 'target' is not set · 284373b7
  Dimitris Lampridis authored 5 years ago
  
  284373b7
- [tools] update syndate field of buildinfo to include synthesis time as well · 116a9bf8
  Dimitris Lampridis authored 5 years ago
  
  116a9bf8
- [hdl][vic] do not mask RISR register. Closes #4 · 1b74c39c
  Dimitris Lampridis authored 5 years ago
  
  1b74c39c
Aug 06, 2019
- [doc] fix address of VIC IVT_RAM. Closes #1 · 63af6eeb
  Dimitris Lampridis authored 5 years ago
  
  63af6eeb
Aug 02, 2019
- [hdl] fix bug in gc_sync_word_rd with wrong signal used for loading the next input · 14e96565
  Dimitris Lampridis authored 5 years ago
  
  14e96565
Aug 01, 2019
- gc_sync_word_*: use the same name to use the same constraints. · cc5228b9
  Tristan Gingold authored 5 years ago
  
  cc5228b9
- Add gc_sync_word_rd core. · c99ecb4c
  Tristan Gingold authored 5 years ago
  
  c99ecb4c
Jul 29, 2019

[hdl] move assertion check from gc_sync_word_wr to gc_pulse_synchronizer · eaacde90
Dimitris Lampridis authored 5 years ago

eaacde90
[hdl] code cleanup of gc_frequency_meter · b814d633
Dimitris Lampridis authored 5 years ago

b814d633

[hdl] add g_SYNC_OUT option to gc_frequency meter. · 686760c9

Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain.

With the new option, if set to TRUE, both outputs will be in the system clock domain.

686760c9

[hdl] re-work gc_sync_word_wr · 13cebbbd

Dimitris Lampridis authored 5 years ago

This commit does three changes to gc_sync_word_wr:

1. It converts it to use internally gc_pulse_synchroniser2
2. It introduces a new "busy" output bit
3. It introduces a new generic, g_AUTO_WR which instructs the core to write a new word continously, without input from the user.

13cebbbd

[hdl] gc_pulse_synchroniser2: add new output port ACK · ba8802fe
Dimitris Lampridis authored 5 years ago

ba8802fe

Jul 24, 2019
- gen_buildinfo: also works in simulation mode. · 5dde6da5
  Tristan Gingold authored 5 years ago
  
  5dde6da5
- [tools] fix mem_init_gen to work with Python3 · 6abae0c0
  Dimitris Lampridis authored 5 years ago
  
  6abae0c0
- add c_DUMMY_WB_SLAVE_D64_IN constant · bee232b2
  Dimitris Lampridis authored 5 years ago
  
  bee232b2
Jul 19, 2019
- wb_vic: add fixed polarity; partial rewrite. · ca0ce6ce
  Tristan Gingold authored 5 years ago
  
  ca0ce6ce
- Document wb_split · 68e1c650
  Tristan Gingold authored 5 years ago
  
  68e1c650
- Add wb_split core. · e8b948ed
  Tristan Gingold authored 5 years ago
  
  e8b948ed
Jul 16, 2019
- Add gen_buildinfo.py file. · ac43a1db
  Tristan Gingold authored 5 years ago
  
  ac43a1db
Jul 15, 2019
- f_string2svl: accept any bound for string parameter. · cd3445d2
  Tristan Gingold authored 5 years ago
  
  cd3445d2
- wishbone_pkg: remove unused variable. · a0a709f0
  Tristan Gingold authored 5 years ago
  
  a0a709f0
Jul 11, 2019
- Mention wb_metadata and add it to the Manifest. · c010febb
  Tristan Gingold authored 5 years ago
  
  c010febb
- Add wb_metadata module. · c0e0cbe7
  Tristan Gingold authored 5 years ago
  
  c0e0cbe7
Jul 10, 2019
- virtex6 fifo: (ug363) RSTREG cannot be used until EN_SYN is TRUE and DO_REG is 1 · dcc7cc33
  Grzegorz Daniluk authored 5 years ago
  
  wr-switch-sw-v6.0
  
  dcc7cc33
Jun 19, 2019
- Move gc_ds182x_readout to a subdir, add README. · de821c1d
  Tristan Gingold authored 5 years ago
  
  de821c1d
- Move gc_ds182x_readout.vhd to a subdirectory. · 2c67ec27
  Tristan Gingold authored 5 years ago
  
  2c67ec27