- Sep 16, 2018
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Tomasz Wlostowski authored
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- Sep 11, 2018
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Tomasz Wlostowski authored
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- Aug 10, 2018
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Dimitris Lampridis authored
hdl: add RLOC constraint to gc_sync_ffs in order to keep the two FFs as close as possible to each other
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- Aug 07, 2018
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Dimitris Lampridis authored
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- Aug 06, 2018
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Dimitris Lampridis authored
genram: automatically pad with zeroes when reading from a mem init file smaller than the memory itself
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- Aug 03, 2018
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Dimitris Lampridis authored
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- Jul 30, 2018
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Dimitris Lampridis authored
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- Jul 27, 2018
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Dimitris Lampridis authored
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- Jun 19, 2018
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- Jun 08, 2018
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Dimitris Lampridis authored
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- May 29, 2018
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Grzegorz Daniluk authored
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- May 02, 2018
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- Mar 25, 2018
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Dimitris Lampridis authored
Apologies for the double renaming, but it occured to me that the constant names were too generic and could cause conflicts.
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Dimitris Lampridis authored
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- Mar 23, 2018
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- Mar 20, 2018
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Dimitris Lampridis authored
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Dimitris Lampridis authored
This is introduced to better match the OHWR VHDL coding style [1]. Old names are preserved for backward compatibility. [1]: https://www.ohwr.org/projects/vhdl-style
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- Mar 19, 2018
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Dimitris Lampridis authored
For the few peripherals where it was being used (eg. uart, spi, etc) the output port has been renamed to "int_o". The only peripheral that was not touched is "wb_eic.vhd", because this one is being used by wbgen, and it would require users to update their wbgen tool as well. So, until a new tool is introduced, wbgen-generated interrupt controllers will have an output port called wb_int_o".
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- Mar 16, 2018
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Tristan Gingold authored
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- Mar 14, 2018
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Dimitris Lampridis authored
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- Mar 09, 2018
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Dimitris Lampridis authored
This reverts commit 49afba43. This change was introduced in the masterFIP branch, but it can break many existing designs, so it is reverted.
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- Mar 08, 2018
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Dimitris Lampridis authored
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The main state machine had an error whereby the wb_cyc and wb_stb outputs were not assigned in the IDLE state. This manifested itself as follows (output from telnet console): %> writereg 1 100 0 # read to illegal address Not acknowledged! %> readreg 1 4 # read from legal address returns NACK Not acknowledged %> readreg 1 4 # next read from legal address returns right data Read data: 01234567 The bug was because the first writereg started a WB transfer from an unexisting address, threw an error and returned to IDLE without releasing the wb_cyc and wb_stb outputs in the process. This meant that on the readreg command, the WB write access would still be in progress and only on the readreg command, an error would clear the wb_cyc and wb_stb, which released the transfer. The error has been fixed by placing the clearing of wb_cyc and wb_stb in the IDLE state.
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- Mar 02, 2018
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- Jan 23, 2018
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Dimitris Lampridis authored
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- Dec 14, 2017
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Maciej Lipinski authored
the wishbone package In wishbone_pkg.vhd, the new g_sdb_name generic was added to xwb_crossbar instead of xwb_sdb_crossbar. Fixed
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- Dec 13, 2017
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- sdb_rom: add parameter g_sdb_name - xwb_sdb_crossbar: add parameter g_sdb_name - wishbone_pkg: f_string_fix_len add parameter justify_right - wishbone_pkg: f_sdb_auto_device add parameter name - wishbone_pkg: f_sdb_auto_bridge add parameter name
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Grzegorz Daniluk authored
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- Nov 28, 2017
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Tomasz Wlostowski authored
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- Oct 11, 2017
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Dimitris Lampridis authored
wishbone/wb_gpio_port: match length of gpio_b to gpio_in when g_num_pins is not an exact multiple of 32. Closes #1532
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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