The previous implementation was introducing latches to the GN4124 core under Xilinx ISE.

Tested and verified to work with the following SPEC-based reference designs:
 - WR
 - MT
 - WRTD

Although not mentioned in section 5.2 of Wishbone B4 specification, when interfacing a pipelined
master to a standard slave, it is also necessary to make sure that if the slave asserts ACK/ERR/RTY
for more than one clock cycle (which a standard slave could do since, according to Rule 3.50 of
Wishbone B4, "the slave deasserts ACK/ERR/RTY in response to the negation of STB"), the master will
still only see a one cycle wide pulse.