Conflicts:

	modules/common/gc_crc_gen.vhd

Conflicts:

	modules/common/Manifest.py
	modules/common/gencores_pkg.vhd

In case the free_clk itself is not running when the lock is lost,
still reset the other clock domains.

Each clock domain needs a separate reset line.
However, one cannot reset only a single domain---that could cause inconsistency
at clock crossing boundaries.
This change splits reset lines per clock domain and centralizes generation.

Updated uses of the wishbone_pkg to use Tom's naming conventions.
Added Manifests for the new files.