This reverts commit 49afba43.

This change was introduced in the masterFIP branch, but it can break many existing designs, so it is reverted.

Theodor-Adrian Stana authored 10 years ago and Dimitris Lampridis committed 7 years ago

The main state machine had an error whereby the wb_cyc and wb_stb
outputs were not assigned in the IDLE state.

This manifested itself as follows (output from telnet console):

%> writereg 1 100 0 # read to illegal address
  Not acknowledged!
%> readreg 1 4 # read from legal address returns NACK
  Not acknowledged
%> readreg 1 4 # next read from legal address returns right data
  Read data: 01234567

The bug was because the first writereg started a WB transfer from
an unexisting address, threw an error and returned to IDLE without
releasing the wb_cyc and wb_stb outputs in the process. This meant
that on the readreg command, the WB write access would still be in
progress and only on the readreg command, an error would clear the
wb_cyc and wb_stb, which released the transfer.

The error has been fixed by placing the clearing of wb_cyc and wb_stb
in the IDLE state.

the wishbone package

In wishbone_pkg.vhd, the new g_sdb_name generic was added to
xwb_crossbar instead of xwb_sdb_crossbar. Fixed

Piotr Miedzik authored 7 years ago and Dimitris Lampridis committed 7 years ago

- sdb_rom: add parameter g_sdb_name
- xwb_sdb_crossbar: add parameter g_sdb_name
- wishbone_pkg: f_string_fix_len add parameter justify_right
- wishbone_pkg: f_sdb_auto_device add parameter name
- wishbone_pkg: f_sdb_auto_bridge add parameter name

wishbone/wb_gpio_port: match length of gpio_b to gpio_in when g_num_pins is not an exact multiple of 32. Closes #1532

They finally don't help much and they break simulation as Modelsim complains
about types conversion.

Fix it the same way as f_x_to_zero() is fixed in wbgen.

It fixes some functions not well understood by Vivado synthesis

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

it was de-asserted at wrong value (too early/late). This was making
to misbehave the modules that depend on this signals.

Conflicts:
	modules/common/gencores_pkg.vhd