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Commit b5fa01bb authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wb_lm32: enabled HW division for WR node profile

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modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
+ 180
− 128
View file @ b5fa01bb
...@@ -88432,6 +88432,8 @@ endmodule ...@@ -88432,6 +88432,8 @@ endmodule
   
   
   
...@@ -88662,8 +88664,10 @@ endmodule ...@@ -88662,8 +88664,10 @@ endmodule
   
   
   
   
...@@ -89681,9 +89685,10 @@ module lm32_mc_arithmetic_wr_node ( ...@@ -89681,9 +89685,10 @@ module lm32_mc_arithmetic_wr_node (
stall_d, stall_d,
kill_x, kill_x,
   
divide_d,
modulus_d,
   
...@@ -89700,8 +89705,9 @@ module lm32_mc_arithmetic_wr_node ( ...@@ -89700,8 +89705,9 @@ module lm32_mc_arithmetic_wr_node (
result_x, result_x,
   
divide_by_zero_x,
   
stall_request_x stall_request_x
); );
...@@ -89715,9 +89721,10 @@ input rst_i; ...@@ -89715,9 +89721,10 @@ input rst_i;
input stall_d; input stall_d;
input kill_x; input kill_x;
   
input divide_d;
input modulus_d;
   
...@@ -89739,9 +89746,10 @@ input [ (32-1):0] operand_1_d; ...@@ -89739,9 +89746,10 @@ input [ (32-1):0] operand_1_d;
output [ (32-1):0] result_x; output [ (32-1):0] result_x;
reg [ (32-1):0] result_x; reg [ (32-1):0] result_x;
   
output divide_by_zero_x;
reg divide_by_zero_x;
   
output stall_request_x; output stall_request_x;
wire stall_request_x; wire stall_request_x;
...@@ -89754,8 +89762,9 @@ reg [ (32-1):0] p; ...@@ -89754,8 +89762,9 @@ reg [ (32-1):0] p;
reg [ (32-1):0] a; reg [ (32-1):0] a;
reg [ (32-1):0] b; reg [ (32-1):0] b;
   
wire [32:0] t;
   
   
reg [ 2:0] state; reg [ 2:0] state;
...@@ -89776,8 +89785,9 @@ assign stall_request_x = state != 3'b000; ...@@ -89776,8 +89785,9 @@ assign stall_request_x = state != 3'b000;
   
   
   
assign t = {p[ 32-2:0], a[ 32-1]} - b;
   
   
...@@ -89804,8 +89814,9 @@ begin ...@@ -89804,8 +89814,9 @@ begin
   
   
   
divide_by_zero_x <= 1'b0;
   
result_x <= { 32{1'b0}}; result_x <= { 32{1'b0}};
state <= 3'b000; state <= 3'b000;
...@@ -89813,8 +89824,9 @@ begin ...@@ -89813,8 +89824,9 @@ begin
else else
begin begin
   
divide_by_zero_x <= 1'b0;
   
case (state) case (state)
3'b000: 3'b000:
...@@ -89826,11 +89838,12 @@ begin ...@@ -89826,11 +89838,12 @@ begin
a <= operand_0_d; a <= operand_0_d;
b <= operand_1_d; b <= operand_1_d;
   
if (divide_d == 1'b1)
state <= 3'b011 ;
if (modulus_d == 1'b1)
state <= 3'b010 ;
...@@ -89859,49 +89872,50 @@ begin ...@@ -89859,49 +89872,50 @@ begin
end end
end end
3'b011 :
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
a <= {a[ 32-2:0], 1'b1};
end
else
begin
p <= {p[ 32-2:0], a[ 32-1]};
a <= {a[ 32-2:0], 1'b0};
end
result_x <= a;
if ((cycles == 32'd0) || (kill_x == 1'b1))
begin
divide_by_zero_x <= b == { 32{1'b0}};
state <= 3'b000;
end
cycles <= cycles - 1'b1;
end
3'b010 :
begin
if (t[32] == 1'b0)
begin
p <= t[31:0];
a <= {a[ 32-2:0], 1'b1};
end
else
begin
p <= {p[ 32-2:0], a[ 32-1]};
a <= {a[ 32-2:0], 1'b0};
end
result_x <= p;
if ((cycles == 32'd0) || (kill_x == 1'b1))
begin
divide_by_zero_x <= b == { 32{1'b0}};
state <= 3'b000;
end
cycles <= cycles - 1'b1;
end
...@@ -90701,10 +90715,11 @@ wire [ 1:0] d_result_sel_1_d; ...@@ -90701,10 +90715,11 @@ wire [ 1:0] d_result_sel_1_d;
wire x_result_sel_csr_d; wire x_result_sel_csr_d;
reg x_result_sel_csr_x; reg x_result_sel_csr_x;
   
wire q_d;
wire x_result_sel_mc_arith_d;
reg x_result_sel_mc_arith_x;
   
...@@ -90917,19 +90932,21 @@ wire [ (32-1):0] multiplier_result_w; ...@@ -90917,19 +90932,21 @@ wire [ (32-1):0] multiplier_result_w;
   
   
   
wire divide_d;
wire divide_q_d;
wire modulus_d;
wire modulus_q_d;
wire divide_by_zero_x;
   
   
   
   
wire mc_stall_request_x;
wire [ (32-1):0] mc_result_x;
   
   
   
...@@ -91096,8 +91113,9 @@ wire interrupt_exception; ...@@ -91096,8 +91113,9 @@ wire interrupt_exception;
   
   
   
wire divide_by_zero_exception;
   
wire system_call_exception; wire system_call_exception;
   
...@@ -91299,8 +91317,9 @@ lm32_decoder_wr_node decoder ( ...@@ -91299,8 +91317,9 @@ lm32_decoder_wr_node decoder (
.d_result_sel_1 (d_result_sel_1_d), .d_result_sel_1 (d_result_sel_1_d),
.x_result_sel_csr (x_result_sel_csr_d), .x_result_sel_csr (x_result_sel_csr_d),
   
.x_result_sel_mc_arith (x_result_sel_mc_arith_d),
   
...@@ -91360,9 +91379,10 @@ lm32_decoder_wr_node decoder ( ...@@ -91360,9 +91379,10 @@ lm32_decoder_wr_node decoder (
   
   
   
.divide (divide_d),
.modulus (modulus_d),
   
.branch (branch_d), .branch (branch_d),
.bi_unconditional (bi_unconditional), .bi_unconditional (bi_unconditional),
...@@ -91522,34 +91542,41 @@ lm32_multiplier multiplier ( ...@@ -91522,34 +91542,41 @@ lm32_multiplier multiplier (
   
   
lm32_mc_arithmetic_wr_node mc_arithmetic (
.clk_i (clk_i),
.rst_i (rst_i),
.stall_d (stall_d),
.kill_x (kill_x),
.divide_d (divide_q_d),
.modulus_d (modulus_q_d),
   
   
   
.operand_0_d (d_result_0),
.operand_1_d (d_result_1),
.result_x (mc_result_x),
.divide_by_zero_x (divide_by_zero_x),
   
.stall_request_x (mc_stall_request_x)
);
   
...@@ -92036,8 +92063,9 @@ begin ...@@ -92036,8 +92063,9 @@ begin
   
   
   
: x_result_sel_mc_arith_x ? mc_result_x
   
: logic_result_x; : logic_result_x;
end end
...@@ -92192,8 +92220,9 @@ assign kill_w = 1'b0 ...@@ -92192,8 +92220,9 @@ assign kill_w = 1'b0
   
   
   
assign divide_by_zero_exception = divide_by_zero_x == 1'b1;
   
   
assign system_call_exception = ( (scall_x == 1'b1) assign system_call_exception = ( (scall_x == 1'b1)
...@@ -92242,8 +92271,9 @@ assign exception_x = (system_call_exception == 1'b1) ...@@ -92242,8 +92271,9 @@ assign exception_x = (system_call_exception == 1'b1)
   
   
   
|| (divide_by_zero_exception == 1'b1)
   
   
...@@ -92299,10 +92329,11 @@ begin ...@@ -92299,10 +92329,11 @@ begin
   
   
   
if (divide_by_zero_exception == 1'b1)
eid_x = 3'h5;
else
   
   
...@@ -92376,10 +92407,11 @@ assign stall_d = (stall_x == 1'b1) ...@@ -92376,10 +92407,11 @@ assign stall_d = (stall_x == 1'b1)
assign stall_x = (stall_m == 1'b1) assign stall_x = (stall_m == 1'b1)
   
|| ( (mc_stall_request_x == 1'b1)
&& (kill_x == 1'b0)
)
   
   
...@@ -92441,8 +92473,9 @@ assign stall_m = (stall_wb_load == 1'b1) ...@@ -92441,8 +92473,9 @@ assign stall_m = (stall_wb_load == 1'b1)
   
   
   
assign q_d = (valid_d == 1'b1) && (kill_d == 1'b0);
   
...@@ -92454,9 +92487,10 @@ assign stall_m = (stall_wb_load == 1'b1) ...@@ -92454,9 +92487,10 @@ assign stall_m = (stall_wb_load == 1'b1)
   
   
   
assign divide_q_d = (divide_d == 1'b1) && (q_d == 1'b1);
assign modulus_q_d = (modulus_d == 1'b1) && (q_d == 1'b1);
   
assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0); assign q_x = (valid_x == 1'b1) && (kill_x == 1'b0);
assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1); assign csr_write_enable_q_x = (csr_write_enable_x == 1'b1) && (q_x == 1'b1);
...@@ -92578,11 +92612,11 @@ assign cfg = { ...@@ -92578,11 +92612,11 @@ assign cfg = {
   
   
   
1'b1,
1'b0,
   
...@@ -92858,8 +92892,9 @@ begin ...@@ -92858,8 +92892,9 @@ begin
branch_target_x <= { (32-2){1'b0}}; branch_target_x <= { (32-2){1'b0}};
x_result_sel_csr_x <= 1'b0; x_result_sel_csr_x <= 1'b0;
   
x_result_sel_mc_arith_x <= 1'b0;
   
...@@ -93000,8 +93035,9 @@ begin ...@@ -93000,8 +93035,9 @@ begin
branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d; branch_target_x <= branch_reg_d == 1'b1 ? bypass_data_0[ ((32-2)+2-1):2] : branch_target_d;
x_result_sel_csr_x <= x_result_sel_csr_d; x_result_sel_csr_x <= x_result_sel_csr_d;
   
x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
   
...@@ -95031,8 +95067,9 @@ module lm32_decoder_wr_node ( ...@@ -95031,8 +95067,9 @@ module lm32_decoder_wr_node (
d_result_sel_1, d_result_sel_1,
x_result_sel_csr, x_result_sel_csr,
   
x_result_sel_mc_arith,
...@@ -95092,9 +95129,10 @@ module lm32_decoder_wr_node ( ...@@ -95092,9 +95129,10 @@ module lm32_decoder_wr_node (
   
   
   
divide,
modulus,
   
branch, branch,
branch_reg, branch_reg,
...@@ -95135,9 +95173,10 @@ reg [ 1:0] d_result_sel_1; ...@@ -95135,9 +95173,10 @@ reg [ 1:0] d_result_sel_1;
output x_result_sel_csr; output x_result_sel_csr;
reg x_result_sel_csr; reg x_result_sel_csr;
   
output x_result_sel_mc_arith;
reg x_result_sel_mc_arith;
   
...@@ -95226,11 +95265,12 @@ wire direction; ...@@ -95226,11 +95265,12 @@ wire direction;
   
   
   
output divide;
wire divide;
output modulus;
wire modulus;
   
output branch; output branch;
wire branch; wire branch;
...@@ -95296,8 +95336,9 @@ wire op_cmpgeu; ...@@ -95296,8 +95336,9 @@ wire op_cmpgeu;
wire op_cmpgu; wire op_cmpgu;
wire op_cmpne; wire op_cmpne;
   
wire op_divu;
   
wire op_lb; wire op_lb;
wire op_lbu; wire op_lbu;
...@@ -95305,8 +95346,9 @@ wire op_lh; ...@@ -95305,8 +95346,9 @@ wire op_lh;
wire op_lhu; wire op_lhu;
wire op_lw; wire op_lw;
   
wire op_modu;
   
   
...@@ -95446,8 +95488,9 @@ assign op_cmpgeu = instruction[ 30:26] == 5'b11100; ...@@ -95446,8 +95488,9 @@ assign op_cmpgeu = instruction[ 30:26] == 5'b11100;
assign op_cmpgu = instruction[ 30:26] == 5'b11101; assign op_cmpgu = instruction[ 30:26] == 5'b11101;
assign op_cmpne = instruction[ 30:26] == 5'b11111; assign op_cmpne = instruction[ 30:26] == 5'b11111;
   
assign op_divu = instruction[ 31:26] == 6'b100011;
   
assign op_lb = instruction[ 31:26] == 6'b000100; assign op_lb = instruction[ 31:26] == 6'b000100;
assign op_lbu = instruction[ 31:26] == 6'b010000; assign op_lbu = instruction[ 31:26] == 6'b010000;
...@@ -95455,8 +95498,9 @@ assign op_lh = instruction[ 31:26] == 6'b000111; ...@@ -95455,8 +95498,9 @@ assign op_lh = instruction[ 31:26] == 6'b000111;
assign op_lhu = instruction[ 31:26] == 6'b001011; assign op_lhu = instruction[ 31:26] == 6'b001011;
assign op_lw = instruction[ 31:26] == 6'b001010; assign op_lw = instruction[ 31:26] == 6'b001010;
   
assign op_modu = instruction[ 31:26] == 6'b110001;
   
   
...@@ -95525,9 +95569,10 @@ assign sext = op_sextb | op_sexth; ...@@ -95525,9 +95569,10 @@ assign sext = op_sextb | op_sexth;
   
   
   
assign divide = op_divu;
assign modulus = op_modu;
   
assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw; assign load = op_lb | op_lbu | op_lh | op_lhu | op_lw;
assign store = op_sb | op_sh | op_sw; assign store = op_sb | op_sh | op_sw;
...@@ -95549,8 +95594,9 @@ begin ...@@ -95549,8 +95594,9 @@ begin
x_result_sel_csr = 1'b0; x_result_sel_csr = 1'b0;
   
x_result_sel_mc_arith = 1'b0;
   
...@@ -95569,20 +95615,25 @@ begin ...@@ -95569,20 +95615,25 @@ begin
x_result_sel_add = 1'b0; x_result_sel_add = 1'b0;
if (op_rcsr) if (op_rcsr)
x_result_sel_csr = 1'b1; x_result_sel_csr = 1'b1;
   
   
else if (divide | modulus)
x_result_sel_mc_arith = 1'b1;
   
   
   
...@@ -95636,9 +95687,10 @@ assign x_bypass_enable = arith ...@@ -95636,9 +95687,10 @@ assign x_bypass_enable = arith
   
   
   
| divide
| modulus
   
modules/wishbone/wb_lm32/lm32.profiles
+ 1
− 1
View file @ b5fa01bb
...@@ -5,4 +5,4 @@ medium_debug CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND ...@@ -5,4 +5,4 @@ medium_debug CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND
medium_icache_debug CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_ICACHE_ENABLED CFG_WITH_DEBUG CFG_INTERRUPTS_ENABLED medium_icache_debug CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_ICACHE_ENABLED CFG_WITH_DEBUG CFG_INTERRUPTS_ENABLED
full CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_INTERRUPTS_ENABLED CFG_MC_DIVIDE_ENABLED CFG_FAST_UNCONDITIONAL_BRANCH CFG_ICACHE_ENABLED CFG_DCACHE_ENABLED CFG_BUS_ERRORS_ENABLED full CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_INTERRUPTS_ENABLED CFG_MC_DIVIDE_ENABLED CFG_FAST_UNCONDITIONAL_BRANCH CFG_ICACHE_ENABLED CFG_DCACHE_ENABLED CFG_BUS_ERRORS_ENABLED
full_debug CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_INTERRUPTS_ENABLED CFG_MC_DIVIDE_ENABLED CFG_FAST_UNCONDITIONAL_BRANCH CFG_ICACHE_ENABLED CFG_DCACHE_ENABLED CFG_BUS_ERRORS_ENABLED CFG_WITH_DEBUG full_debug CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_INTERRUPTS_ENABLED CFG_MC_DIVIDE_ENABLED CFG_FAST_UNCONDITIONAL_BRANCH CFG_ICACHE_ENABLED CFG_DCACHE_ENABLED CFG_BUS_ERRORS_ENABLED CFG_WITH_DEBUG
wr_node CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_INTERRUPTS_ENABLED CFG_IRAM_ENABLED wr_node CFG_PL_MULTIPLY_ENABLED CFG_PL_BARREL_SHIFT_ENABLED CFG_SIGN_EXTEND_ENABLED CFG_INTERRUPTS_ENABLED CFG_IRAM_ENABLED CFG_MC_DIVIDE_ENABLED
\ No newline at end of file \ No newline at end of file
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