altera pcie: add arria5 + remove generate files

platform/altera/wb_pcie/.gitignore

+# quartus droppings
+db/
+greybox_tmp/
+# arria5 pcie reconfig core
+arria5_pcie_reconf_sim/
+arria5_pcie_reconf/
+arria5_pcie_reconf.bsf
+arria5_pcie_reconf.cmp
+arria5_pcie_reconf.ppf
+arria5_pcie_reconf.qip
+arria5_pcie_reconf_sim
+arria5_pcie_reconf.sip
+arria5_pcie_reconf.spd
+arria5_pcie_reconf.vhd
+# arria5 pcie hard ip core
+arria5_pcie_hip_example_design/
+arria5_pcie_hip_sim/
+arria5_pcie_hip/
+arria5_pcie_hip.bsf
+arria5_pcie_hip.cmp
+arria5_pcie_hip.ppf
+arria5_pcie_hip.qip
+arria5_pcie_hip_sim
+arria5_pcie_hip.sip
+arria5_pcie_hip.spd
+arria5_pcie_hip.vhd
+# arria2 pcie reconfig core
+arria2_pcie_reconf.cmp
+arria2_pcie_reconf.qip
+arria2_pcie_reconf.vhd
+# arria2 pcie hard ip core
+ip_compiler_for_pci_express-library/
+arria2_pcie_hip_examples/
+arria2_pcie_hip.bsf
+arria2_pcie_hip.ppf
+arria2_pcie_hip.ppx
+arria2_pcie_hip.qip
+arria2_pcie_hip.sdc
+arria2_pcie_hip.tcl
+arria2_pcie_hip.vhd
+arria2_pcie_hip_core.cmp
+arria2_pcie_hip_core.vhd
+arria2_pcie_hip_serdes.vhd
+arria2_pcie_hip_serdes.cmp

platform/altera/wb_pcie/Manifest.py

-files = [
-  "altera_reconfig.vhd",
-  "altera_pcie_serdes.vhd",
-  "altera_pcie_core.vhd",
-  "altera_pcie.vhd",
-  "pcie_32to64.vhd",
-  "pcie_64to32.vhd",
-  "pcie_altera.vhd",
-  "pcie_tlp.vhd",
-  "pcie_wb.vhd",
-  "pcie_wb_pkg.vhd",
-  "ip_compiler_for_pci_express-library/altpcie_rs_serdes.v"]
+def __helper():
+  files = [
+    "pcie_32to64.vhd",
+    "pcie_64to32.vhd",
+    "pcie_altera.vhd",
+    "pcie_tlp.vhd",
+    "pcie_wb.vhd",
+    "pcie_wb_pkg.vhd"]
+  if syn_device[:1] == "5":    files.extend(["arria5_pcie.qip"])
+  if syn_device[:4] == "ep2a": files.extend(["arria2_pcie.qip"])
+  return files
+
+files = __helper()

platform/altera/wb_pcie/altera_pcie.qip

-set_global_assignment -name IP_TOOL_NAME "IP Compiler for PCI Express"
-set_global_assignment -name IP_TOOL_VERSION "12.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie.vhd"]
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_pcie_core.vhd"]
-set_global_assignment -name SEARCH_PATH  [file join $::quartus(qip_path) "." ]
-set_global_assignment -name SEARCH_PATH [file join $::quartus(qip_path) ip_compiler_for_pci_express-library ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_16p.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp4x125_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_12500.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x8d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_250_100.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy0.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy1_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_confctrl.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_4sgx.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x1_15625.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_align.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pclk_pll.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp_dcram.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x8d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x1_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x8_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x1d_gen1_16p.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_pexreg.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_12500.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp1x125_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_256_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_trans.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_64b_x4_pipen1b.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexp64_dlink.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy2.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_15625_125.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_hip_pipen1b.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcierd_reconfig_clk_pll.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x4d_10000.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x8d_gen2_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_100_125.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2sgx_x1d_10000.v ]
-set_global_assignment -name OCP_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/pciexpx8f_ltssm.ocp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy3_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy5_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_2agx_x1d_gen1_16p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_phy4_62p5.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_rs_serdes.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_phasefifo.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x1d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_4sgx_x4d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_serdes_3cgx_x2d_gen1_08p.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) ip_compiler_for_pci_express-library/altpcie_pll_125_250.v ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.cmp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_core.vho ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_dma_descriptor.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_dma_dt.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_dma_prg_reg.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_rc_slave.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_read_dma_requester.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcie_write_dma_requester.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altpcierd_example_app_chaining.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/init_ram.hex ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/init_ram.mif ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/altpcietb_bfm_driver_chaining.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/init_ram.hex ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/init_ram.mif ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/runtb.bat ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/runtb.do ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/runtb.sh ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/sim_filelist ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/testbench/altera_pcie_chaining_testbench.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_pipen1b.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_plus.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_rs_hip.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.qpf ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.qsf ]
-set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) altera_pcie.sdc ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.tcl ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/chaining_dma/altera_pcie_example_chaining_top.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/common ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/common/testbench ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_fifo.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_fifo_lkahd.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_msibridge.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_npbypassctl.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_rx.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_rxbridge.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_sideband.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_top.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_tx.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_tx_pktordering.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_txbridge.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altpcierd_icm_txbridge_withbypass.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_examples/incremental_compile_module/altera_pcie_icm.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie_serdes.vhd ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.ppx ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.ppf ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.cmp ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.bsf ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.qip ]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) altera_pcie.html ]

platform/altera/wb_pcie/altera_pcie.sdc

-# The refclk assignment may need to be renamed to match design top level port name.
-# May be desireable to move refclk assignment to a top level SDC file.
-create_clock -period "100 MHz" -name {refclk} {refclk}
-create_clock -period "100 MHz" -name {fixedclk_serdes} {fixedclk_serdes}
-# testin bits are either static or treated asynchronously, cut the paths.
-set_false_path -to [get_pins -hierarchical {*hssi_pcie_hip|testin[*]} ]
-# SERDES Digital Reset inputs are asynchronous
-set_false_path -to {*|altera_pcie_serdes:serdes|*|tx_digitalreset_reg0c[0]}
-set_false_path -to {*|altera_pcie_serdes:serdes|*|rx_digitalreset_reg0c[0]}
-#
-# The following multicycle path constraints are only valid if the logic use to sample the tl_cfg_ctl and tl_cfg_sts signals 
-# are as designed in the Altera provided files altpcierd_tl_cfg_sample.v and altpcierd_tl_cfg_sample.vhd   
-# 
-# These constraints are only valid when the altpcierd_tl_cfg_sample module or entity is used with the PCI Express
-# Hard IP block in Stratix IV, Arria II, Cyclone IV and HardCopy IV devices. 
-#
-set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr_hip}] 2
-set_multicycle_path -end -hold  -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_wr_hip}] 1
-set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_hip[*]}] 3
-set_multicycle_path -end -hold  -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_ctl_hip[*]}] 2
-#
-set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr_hip}] 2
-set_multicycle_path -end -hold  -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_wr_hip}] 1
-set_multicycle_path -end -setup -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_hip[*]}] 3
-set_multicycle_path -end -hold  -from [get_keepers {*|altera_pcie_core:wrapper|altpcie_hip_pipen1b:altpcie_hip_pipen1b_inst|tl_cfg_sts_hip[*]}] 2

platform/altera/wb_pcie/altera_reconfig.qip

-set_global_assignment -name IP_TOOL_NAME "ALTGX_RECONFIG"
-set_global_assignment -name IP_TOOL_VERSION "11.1"
-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altera_reconfig.vhd"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altera_reconfig.cmp"]

platform/altera/wb_pcie/arria2.tcl

+set files { arria2_pcie_hip arria2_pcie_reconf }
+
+set dir [file dirname [info script]]
+post_message "Testing for megawizard regeneration in $dir:$files"
+
+foreach i $files {
+  if {![file exists "$dir/$i.qip"] || [file mtime "$dir/$i.txt"] > [file mtime "$dir/$i.qip"]} {
+    post_message "Regenerating $i using qmegawiz"
+    file copy -force "$dir/$i.txt" "$dir/$i.vhd"
+# disable error reporting as arria2 hip is broken
+#    set sf [open "| qmegawiz -silent $dir/$i.vhd" "r"]
+#    while {[gets $sf line] >= 0} { post_message "$line" }
+#    close $sf
+    qexec "qmegawiz -silent $dir/$i.vhd"
+    file mtime "$dir/$i.qip" [file mtime "$dir/$i.vhd"]
+  }
+}

platform/altera/wb_pcie/arria2_pcie.qip

+set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_pcie_hip.qip"]
+set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria2_pcie_reconf.qip"]

platform/altera/wb_pcie/arria2_pcie_reconf.txt

+-- megafunction wizard: %ALTGX_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: alt2gxb_reconfig 
+
+--alt2gxb_reconfig BASE_PORT_WIDTH=1 CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Arria II GX" ENABLE_BUF_CAL="TRUE" ENABLE_CHL_ADDR_FOR_ANALOG_CTRL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 READ_BASE_PORT_WIDTH=1 RECONFIG_FROMGXB_WIDTH=17 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_mode_sel reconfig_togxb
+--VERSION_BEGIN 12.1SP1 cbx_alt2gxb_reconfig 2013:01:31:18:04:54:SJ cbx_alt_cal 2013:01:31:18:04:54:SJ cbx_alt_dprio 2013:01:31:18:04:54:SJ cbx_altsyncram 2013:01:31:18:04:54:SJ cbx_cycloneii 2013:01:31:18:04:54:SJ cbx_lpm_add_sub 2013:01:31:18:04:54:SJ cbx_lpm_compare 2013:01:31:18:04:54:SJ cbx_lpm_counter 2013:01:31:18:04:54:SJ cbx_lpm_decode 2013:01:31:18:04:54:SJ cbx_lpm_mux 2013:01:31:18:04:54:SJ cbx_lpm_shiftreg 2013:01:31:18:04:54:SJ cbx_mgl 2013:01:31:19:27:12:SJ cbx_stratix 2013:01:31:18:04:54:SJ cbx_stratixii 2013:01:31:18:04:54:SJ cbx_stratixiii 2013:01:31:18:04:54:SJ cbx_stratixv 2013:01:31:18:04:54:SJ cbx_util_mgl 2013:01:31:18:04:54:SJ  VERSION_END
+
+
+--alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
+--VERSION_BEGIN 12.1SP1 cbx_alt_dprio 2013:01:31:18:04:54:SJ cbx_cycloneii 2013:01:31:18:04:54:SJ cbx_lpm_add_sub 2013:01:31:18:04:54:SJ cbx_lpm_compare 2013:01:31:18:04:54:SJ cbx_lpm_counter 2013:01:31:18:04:54:SJ cbx_lpm_decode 2013:01:31:18:04:54:SJ cbx_lpm_shiftreg 2013:01:31:18:04:54:SJ cbx_mgl 2013:01:31:19:27:12:SJ cbx_stratix 2013:01:31:18:04:54:SJ cbx_stratixii 2013:01:31:18:04:54:SJ  VERSION_END
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADCE NUMERIC "0"
+-- Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
+-- Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
+-- Retrieval info: PRIVATE: PMA NUMERIC "1"
+-- Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: CONSTANT: BASE_PORT_WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
+-- Retrieval info: CONSTANT: ENABLE_CHL_ADDR_FOR_ANALOG_CTRL STRING "TRUE"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
+-- Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
+-- Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
+-- Retrieval info: CONSTANT: READ_BASE_PORT_WIDTH NUMERIC "1"
+-- Retrieval info: CONSTANT: enable_buf_cal STRING "true"
+-- Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "17"
+-- Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
+-- Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 INPUT NODEFVAL "reconfig_fromgxb[16..0]"
+-- Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
+-- Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
+-- Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
+-- Retrieval info: CONNECT: @reconfig_mode_sel 0 0 3 0 GND 0 0 3 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL arria2_pcie_reconf_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: lpm

platform/altera/wb_pcie/arria5.tcl

+set files { arria5_pcie_hip arria5_pcie_reconf }
+
+set dir [file dirname [info script]]
+post_message "Testing for megawizard regeneration in $dir:$files"
+
+foreach i $files {
+  if {![file exists "$dir/$i.qip"] || [file mtime "$dir/$i.txt"] > [file mtime "$dir/$i.qip"]} {
+    post_message "Regenerating $i using qmegawiz"
+    file copy -force "$dir/$i.txt" "$dir/$i.vhd"
+    set sf [open "| qmegawiz -silent $dir/$i.vhd" "r"]
+    while {[gets $sf line] >= 0} { post_message "$line" }
+    close $sf
+    file mtime "$dir/$i.qip" [file mtime "$dir/$i.vhd"]
+  }
+}

platform/altera/wb_pcie/arria5_pcie.qip

+set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_pcie_hip.qip"]
+set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) "arria5_pcie_reconf.qip"]

platform/altera/wb_pcie/arria5_pcie_reconf.txt

+-- megafunction wizard: %Transceiver Reconfiguration Controller v12.1%
+-- Retrieval info: <instance entity-name="alt_xcvr_reconfig" version="12.1" >
+-- Retrieval info: 	<generic name="device_family" value="Arria V" />
+-- Retrieval info: 	<generic name="number_of_reconfig_interfaces" value="5" />
+-- Retrieval info: 	<generic name="gui_split_sizes" value="" />
+-- Retrieval info: 	<generic name="enable_offset" value="1" />
+-- Retrieval info: 	<generic name="enable_dcd" value="0" />
+-- Retrieval info: 	<generic name="enable_dcd_power_up" value="1" />
+-- Retrieval info: 	<generic name="enable_analog" value="1" />
+-- Retrieval info: 	<generic name="enable_eyemon" value="0" />
+-- Retrieval info: 	<generic name="enable_dfe" value="0" />
+-- Retrieval info: 	<generic name="enable_adce" value="0" />
+-- Retrieval info: 	<generic name="enable_mif" value="0" />
+-- Retrieval info: 	<generic name="gui_enable_pll" value="0" />
+-- Retrieval info: 	<generic name="gui_cal_status_port" value="false" />
+-- Retrieval info: 	<generic name="AUTO_MGMT_CLK_CLK_CLOCK_RATE" value="-1" />
+-- Retrieval info: </instance>