xwb_spi: fixed address size bug

modules/wishbone/wb_spi/wb_spi.vhd

@@ -9,7 +9,7 @@ entity wb_spi is
     clk_sys_i : in std_logic;
     rst_n_i   : in std_logic;
 
-    wb_adr_i : in  std_logic_vector(4 downto 0);
+    wb_adr_i : in  std_logic_vector(2 downto 0);
     wb_dat_i : in  std_logic_vector(31 downto 0);
     wb_dat_o : out std_logic_vector(31 downto 0);
     wb_sel_i : in  std_logic_vector(3 downto 0);
@@ -52,17 +52,18 @@ architecture rtl of wb_spi is
   end component;
 
   signal wb_rst : std_logic;
-  
-  
+  signal core_addr : std_logic_vector(4 downto 0);
 begin  -- rtl
 
   wb_rst <= not rst_n_i;
 
+  core_addr <= wb_adr_i & "00";
+  
   Wrapped_SPI : spi_top
     port map (
       wb_clk_i   => clk_sys_i,
       wb_rst_i   => wb_rst,
-      wb_adr_i   => wb_adr_i,
+      wb_adr_i   => core_addr,
       wb_dat_i   => wb_dat_i,
       wb_dat_o   => wb_dat_o,
       wb_sel_i   => wb_sel_i,