xwb_gpio_port: port size bugfix

modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd

@@ -42,7 +42,7 @@ architecture rtl of xwb_gpio_port is
       wb_sel_i   : in    std_logic;
       wb_stb_i   : in    std_logic;
       wb_we_i    : in    std_logic;
-      wb_adr_i   : in    std_logic_vector(2 downto 0);
+      wb_adr_i   : in    std_logic_vector(5 downto 0);
       wb_dat_i   : in    std_logic_vector(31 downto 0);
       wb_dat_o   : out   std_logic_vector(31 downto 0);
       wb_ack_o   : out   std_logic;
@@ -71,7 +71,7 @@ begin  -- rtl
       wb_cyc_i  => slave_i.cyc,
       wb_stb_i  => slave_i.stb,
       wb_we_i   => slave_i.we,
-      wb_adr_i  => slave_i.adr(2 downto 0),
+      wb_adr_i  => slave_i.adr(5 downto 0),
       wb_dat_i  => slave_i.dat(31 downto 0),
       wb_dat_o  => slave_o.dat(31 downto 0),
       wb_ack_o  => slave_o.ack,