wishbone: wb_spi: added WB slave adapter and xwb_ wrapper

modules/wishbone/wb_spi/wb_spi.vhd

@@ -4,21 +4,25 @@ use ieee.std_logic_1164.all;
 use work.wishbone_pkg.all;
 
 entity wb_spi is
-
+  generic (
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD
+    );
   port(
     clk_sys_i : in std_logic;
     rst_n_i   : in std_logic;
 
-    wb_adr_i : in  std_logic_vector(2 downto 0);
-    wb_dat_i : in  std_logic_vector(31 downto 0);
-    wb_dat_o : out std_logic_vector(31 downto 0);
-    wb_sel_i : in  std_logic_vector(3 downto 0);
-    wb_stb_i : in  std_logic;
-    wb_cyc_i : in  std_logic;
-    wb_we_i  : in  std_logic;
-    wb_ack_o : out std_logic;
-    wb_err_o : out std_logic;
-    wb_int_o : out std_logic;
+    wb_adr_i   : in  std_logic_vector(4 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_cyc_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_err_o   : out std_logic;
+    wb_int_o   : out std_logic;
+    wb_stall_o : out std_logic;
 
     pad_cs_o   : out std_logic_vector(7 downto 0);
     pad_sclk_o : out std_logic;
@@ -51,28 +55,59 @@ architecture rtl of wb_spi is
       miso_pad_i : in  std_logic);
   end component;
 
-  signal wb_rst : std_logic;
-  signal core_addr : std_logic_vector(4 downto 0);
-begin  -- rtl
+  signal rst : std_logic;
 
-  wb_rst <= not rst_n_i;
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
 
-  core_addr <= wb_adr_i & "00";
+  signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
+
+begin
   
-  Wrapped_SPI : spi_top
+  resized_addr(4 downto 0)                          <= wb_adr_i;
+  resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
+
+  U_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => BYTE,
+      g_slave_use_struct   => false,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      master_i   => wb_out,
+      master_o   => wb_in,
+      sl_adr_i   => resized_addr,
+      sl_dat_i   => wb_dat_i,
+      sl_sel_i   => wb_sel_i,
+      sl_cyc_i   => wb_cyc_i,
+      sl_stb_i   => wb_stb_i,
+      sl_we_i    => wb_we_i,
+      sl_dat_o   => wb_dat_o,
+      sl_ack_o   => wb_ack_o,
+      sl_stall_o => wb_stall_o,
+      sl_int_o   => wb_int_o,
+      sl_err_o   => wb_err_o);
+
+  rst <= not rst_n_i;
+
+  Wrapped_SPI : spi_top                 -- byte-aligned
     port map (
       wb_clk_i   => clk_sys_i,
-      wb_rst_i   => wb_rst,
-      wb_adr_i   => core_addr,
-      wb_dat_i   => wb_dat_i,
-      wb_dat_o   => wb_dat_o,
-      wb_sel_i   => wb_sel_i,
-      wb_stb_i   => wb_stb_i,
-      wb_cyc_i   => wb_cyc_i,
-      wb_we_i    => wb_we_i,
-      wb_ack_o   => wb_ack_o,
-      wb_err_o   => wb_err_o,
-      wb_int_o   => wb_int_o,
+      wb_rst_i   => rst,
+      wb_adr_i   => wb_in.adr(4 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_cyc_i   => wb_in.cyc,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_err_o   => wb_out.err,
+      wb_int_o   => wb_out.int,
       ss_pad_o   => pad_cs_o,
       sclk_pad_o => pad_sclk_o,
       mosi_pad_o => pad_mosi_o,

modules/wishbone/wb_spi/xwb_spi.vhd

@@ -5,7 +5,8 @@ use work.wishbone_pkg.all;
 
 entity xwb_spi is
   generic(
-    g_interface_mode : t_wishbone_interface_mode := CLASSIC
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD
     );
 
   port(
@@ -27,60 +28,53 @@ end xwb_spi;
 
 architecture rtl of xwb_spi is
 
-  component spi_top
+  component wb_spi
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity);
     port (
-      wb_clk_i : in  std_logic;
-      wb_rst_i : in  std_logic;
-      wb_adr_i : in  std_logic_vector(4 downto 0);
-      wb_dat_i : in  std_logic_vector(31 downto 0);
-      wb_dat_o : out std_logic_vector(31 downto 0);
-      wb_sel_i : in  std_logic_vector(3 downto 0);
-      wb_stb_i : in  std_logic;
-      wb_cyc_i : in  std_logic;
-      wb_we_i  : in  std_logic;
-      wb_ack_o : out std_logic;
-      wb_err_o : out std_logic;
-      wb_int_o : out std_logic;
-
-      ss_pad_o   : out std_logic_vector(7 downto 0);
-      sclk_pad_o : out std_logic;
-      mosi_pad_o : out std_logic;
-      miso_pad_i : in  std_logic);
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_cyc_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_err_o   : out std_logic;
+      wb_int_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      pad_cs_o   : out std_logic_vector(7 downto 0);
+      pad_sclk_o : out std_logic;
+      pad_mosi_o : out std_logic;
+      pad_miso_i : in  std_logic);
   end component;
-
-  signal wb_rst    : std_logic;
-  signal core_addr : std_logic_vector(4 downto 0);
   
-begin  -- rtl
-
-  gen_test_mode : if(g_interface_mode /= CLASSIC) generate
-    assert false report "xwb_spi: this module can only work with CLASSIC wishbone interface" severity failure;
-  end generate gen_test_mode;
-
-  wb_rst <= not rst_n_i;
+begin
 
-  core_addr <= slave_i.adr(2 downto 0) & "00";
-
-  Wrapped_SPI : spi_top
+  U_Wrapped_SPI: wb_spi
+    generic map (
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity)
     port map (
-      wb_clk_i   => clk_sys_i,
-      wb_rst_i   => wb_rst,
-      wb_adr_i   => core_addr,
-      wb_dat_i   => slave_i.dat(31 downto 0),
-      wb_dat_o   => slave_o.dat(31 downto 0),
-      wb_sel_i   => slave_i.sel(3 downto 0),
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      wb_adr_i   => slave_i.adr(4 downto 0),
+      wb_dat_i   => slave_i.dat,
+      wb_dat_o   => slave_o.dat,
+      wb_sel_i   => slave_i.sel,
       wb_stb_i   => slave_i.stb,
       wb_cyc_i   => slave_i.cyc,
       wb_we_i    => slave_i.we,
       wb_ack_o   => slave_o.ack,
       wb_err_o   => slave_o.err,
       wb_int_o   => slave_o.int,
-      ss_pad_o   => pad_cs_o,
-      sclk_pad_o => pad_sclk_o,
-      mosi_pad_o => pad_mosi_o,
-      miso_pad_i => pad_miso_i);
-
-  slave_o.rty   <= '0';
-  slave_o.stall <= '0';
-
+      wb_stall_o => slave_o.stall,
+      pad_cs_o   => pad_cs_o,
+      pad_sclk_o => pad_sclk_o,
+      pad_mosi_o => pad_mosi_o,
+      pad_miso_i => pad_miso_i);
+  
 end rtl;