[hdl] use new gc_sync for pulse synchroniser as well.

The main reason for doing this is so that all our sync modules are based directly on
gc_sync (instead of using it indirectly through gc_sync_ffs).

Another benefit of this is that the feedback loop of the pulse synchroniser will now be two clock
cycles shorter (one input clock cycle + one output clock cycle), since gc_sync_ffs is using one
more flip-flop compared to gc_sync.

This will also reduce the number of warnings in various synthesis and simulation tools, since
gc_pulse_syncrhonizer is also used by the gc_sync_word modules, as well as the async dual clock
FIFOs.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

modules/common/gc_pulse_synchronizer2.vhd

@@ -63,23 +63,27 @@ architecture rtl of gc_pulse_synchronizer2 is
 
 begin  -- rtl
 
-  cmp_in2out_sync : gc_sync_ffs
+  cmp_in2out_sync : gc_sync
     port map (
-      clk_i    => clk_out_i,
-      rst_n_i  => rst_out_n_i,
-      data_i   => in_ext,
-      synced_o => out_ext,
-      npulse_o => open,
-      ppulse_o => q_p_o);
-
-  cmp_out2in_sync : gc_sync_ffs
+      clk_i     => clk_out_i,
+      rst_n_a_i => rst_out_n_i,
+      d_i       => in_ext,
+      q_o       => out_ext);
+
+
+  cmp_pulse_out : gc_edge_detect
+    port map (
+      clk_i   => clk_out_i,
+      rst_n_i => rst_out_n_i,
+      data_i  => out_ext,
+      pulse_o => q_p_o);
+
+  cmp_out2in_sync : gc_sync
     port map (
-      clk_i    => clk_in_i,
-      rst_n_i  => rst_in_n_i,
-      data_i   => out_ext,
-      synced_o => out_feedback,
-      npulse_o => open,
-      ppulse_o => open);
+      clk_i     => clk_in_i,
+      rst_n_a_i => rst_in_n_i,
+      d_i       => out_ext,
+      q_o       => out_feedback);
 
   p_input_ack : process(clk_in_i)
   begin