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Commit 4afe89ad authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Tomasz Wlostowski
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genrams: now distinguishes between altera/xilinx functional models for simulation

parent c86bf02e
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...@@ -61,12 +61,14 @@ def __import_coregen_files(): ...@@ -61,12 +61,14 @@ def __import_coregen_files():
## "Normal" manifest ## ## "Normal" manifest ##
############################## ##############################
print ("[genrams] target = " + target) print ("[genrams] action = " + action + ", target = " + target)
if (target == "altera"): if (target == "altera"):
modules = {"local" : "altera"} modules = {"local" : "altera"}
elif (target == "xilinx"): elif (target == "xilinx" and action == "synthesis"):
__import_coregen_files() __import_coregen_files()
modules = {"local" : ["xilinx", "coregen_ip/blk_mem_gen_v4_1", "coregen_ip/fifo_generator_v6_1"]} modules = {"local" : ["xilinx", "coregen_ip/blk_mem_gen_v4_1", "coregen_ip/fifo_generator_v6_1"]}
elif (target == "xilinx" and action == "simulation"):
modules = {"local" : ["xilinx", "xilinx/sim_stub"]}
else: else:
modules = {"local" : "altera"} modules = {"local" : "altera"}
\ No newline at end of file
files = ["dummy.vhd"]
library = "fifo_generator_v6_1"
\ No newline at end of file
entity xilinx_dummy_sim is
end xilinx_dummy_sim;
\ No newline at end of file
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