Merge branch 'mat-wbgenplus' into generic_fifo_160105

modules/wishbone/Manifest.py

@@ -20,7 +20,8 @@ modules =  { "local" : [
   "wb_spi_flash",
 	"wb_simple_pwm",
   "wb_i2c_bridge",
-  "wbgen2"
+  "wbgen2",
+  "wbgenplus", 	
   ]}
 
 files = [

modules/wishbone/wbgenplus/Manifest.py

+files = ["wb_skidpad.vhd",
+         "wbgenplus_pkg.vhd",
+
+]
+

modules/wishbone/wbgenplus/wb_skidpad.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity wb_skidpad is
+generic(
+   g_adrbits   : natural   := 32 --Number of bits in adr
+    
+);
+Port(
+   clk_i        : std_logic;      
+   rst_n_i      : std_logic;             
+  
+   push_i       : in  std_logic;  
+   pop_i        : in  std_logic;  
+   full_o       : out std_logic;  
+   empty_o      : out std_logic;  
+
+   adr_i        : in  std_logic_vector(g_adrbits-1 downto 0);
+   dat_i        : in  std_logic_vector(32-1 downto 0);
+   sel_i        : in  std_logic_vector(4-1 downto 0);  
+   we_i         : in  std_logic;
+
+   adr_o        : out std_logic_vector(g_adrbits-1 downto 0);
+   dat_o        : out std_logic_vector(32-1 downto 0);
+   sel_o        : out std_logic_vector(4-1 downto 0);  
+   we_o         : out std_logic
+ 
+   
+);
+end wb_skidpad;
+
+architecture rtl of wb_skidpad is
+
+  signal s_full,  s_valid : std_logic;
+  signal r_full0, r_full1 : std_logic := '0';
+  signal r_buff0, r_buff1 : std_logic_vector(g_adrbits + 32 + 4 + 1 -1 downto 0);
+  signal s_mux            : std_logic_vector(g_adrbits + 32 + 4 + 1 -1 downto 0);
+   
+begin
+
+  s_valid <= r_full1 or  r_full0;
+  s_full  <= r_full1 and r_full0;
+
+  control : process(clk_i, rst_n_i) is
+  begin
+    if rst_n_i = '0' then
+      r_full0 <= '0';
+      r_full1 <= '0';
+    elsif rising_edge(clk_i) then
+      r_full0 <= push_i or s_full;
+      r_full1 <= not pop_i and s_valid;
+    end if;
+  end process;
+  
+  bulk : process(clk_i) is
+  begin
+    if rising_edge(clk_i) then
+      if s_full = '0' then
+        r_buff0 <= adr_i & dat_i & sel_i & we_i;
+      end if;
+      if r_full1 = '0' then      
+        r_buff1 <= r_buff0;
+      end if;
+    end if;
+  end process;
+  
+  s_mux <= r_buff1 when r_full1='1' else r_buff0;
+  adr_o <= s_mux(37+g_adrbits-1 downto 37);
+  dat_o <= s_mux(36 downto 5);
+  sel_o <= s_mux(4 downto 1);
+  we_o  <= s_mux(0);
+  
+  full_o  <= s_full;
+  empty_o <= not s_valid;
+  
+end rtl;

modules/wishbone/wbgenplus/wbgenplus_pkg.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package wbgenplus_pkg is
+
+  component wb_skidpad is
+  generic(
+     g_adrbits   : natural   := 32 --Number of bits in adr
+  );
+  Port(
+     clk_i        : std_logic;
+     rst_n_i      : std_logic;             
+    
+     push_i       : in  std_logic;
+     pop_i        : in  std_logic;
+     full_o       : out std_logic;
+     empty_o      : out std_logic;  
+
+     adr_i        : in  std_logic_vector(g_adrbits-1 downto 0);
+     dat_i        : in  std_logic_vector(32-1 downto 0);
+     sel_i        : in  std_logic_vector(4-1 downto 0);  
+     we_i         : in  std_logic;
+
+     adr_o        : out std_logic_vector(g_adrbits-1 downto 0);
+     dat_o        : out std_logic_vector(32-1 downto 0);
+     sel_o        : out std_logic_vector(4-1 downto 0);  
+     we_o         : out std_logic
+   
+     
+  );
+  end component;
+
+  type matrix is array(natural range <>, natural range <>) of std_logic;
+
+  -- assign row
+
+  function mrst(slm : matrix) return matrix;
+
+  -- assign row
+
+  ---function mset(slm : matrix; slv : std_logic_vector; rowindex : natural) return matrix;
+
+  procedure mset(signal slm : out matrix; slv : std_logic_vector; rowindex : natural);
+
+  procedure mset_no_rng(signal slm : out matrix; slv : std_logic_vector; rowindex : natural);
+
+  -- get std logic vector from matrix row
+
+  function mget(slm : matrix; rowindex : natural) return std_logic_vector;
+
+  -- flatten matrix to std logic vector
+
+  function mflat(slm : matrix) return std_logic_vector;
+
+  -- inflate std logic vector to matrix 
+  function minfl(slm : matrix; slv : std_logic_vector ) return matrix;
+
+  --  inflate std logic vector to m x n matrix
+
+  function minflmn(slv : std_logic_vector; col_len : natural; row_len : natural) return matrix;
+
+end wbgenplus_pkg;
+
+package body wbgenplus_pkg is
+
+  function mrst(slm : matrix) return matrix is
+    variable res : matrix(slm'length(1)-1 downto 0, slm'length(2)-1 downto 0);
+    variable row, col : natural := 0;      
+    constant row_len : natural := slm'length(2);
+    constant col_len : natural := slm'length(1);
+  begin
+    for row in 0 to col_len-1 loop
+      for col in 0 to row_len-1 loop
+        res(row, col) := '0';
+      end loop;
+    end loop;
+    return res;		
+  end function;
+
+  
+  procedure mset(signal slm : out matrix; slv : std_logic_vector; rowindex : natural) is
+    variable i : natural := 0;
+  begin
+    for i in slv'range loop
+      slm(rowindex, i) <= slv(i);
+    end loop;	
+  end procedure;
+
+  procedure mset_no_rng(signal slm : out matrix; slv : std_logic_vector; rowindex : natural) is
+    variable i : natural := 0;
+    variable j : natural := 0;
+  begin
+    j := 0;
+    for i in slv'range loop
+      slm(rowindex, j) <= slv(i);
+      j := j+1;
+    end loop;	
+  end procedure;
+  
+
+  -- set matrix row
+--     function mset(slm : matrix; slv : std_logic_vector; rowindex : natural) return matrix is
+--      variable i : natural := 0;
+--      variable res : matrix(slm'length(1)-1 downto 0, slm'length(2)-1 downto 0);
+--     begin
+--      res := slm;
+--      for i in slv'range loop
+--        res(rowindex, i) := slv(i);
+--      end loop;
+--      return res;		
+--     end function;
+
+  
+  -- get matrix row
+  function mget(slm : matrix; rowindex : natural) return std_logic_vector is
+    variable i : natural := 0;
+    variable slv : std_logic_vector(slm'high(2) downto 0);
+  begin
+    for i in slv'range loop
+      slv(i)  := slm(rowindex, i);
+    end loop;
+    return slv;
+  end function;
+
+  
+  -- flatten matrix to std logic vector
+  function mflat(slm : matrix) return std_logic_vector is
+    constant row_len : natural := slm'length(2);
+    constant col_len : natural := slm'length(1);
+    variable res : std_logic_vector(col_len*row_len-1 downto 0);  
+  begin
+    for row in 0 to col_len-1 loop
+      for col in 0 to row_len-1 loop
+        res(row*row_len+col)  := slm(row, col);
+      end loop;
+    end loop;
+    return res;
+  end function;
+
+
+  -- inflate std logic vector to matrix
+  function minfl(slm : matrix; slv : std_logic_vector) return matrix is
+    constant row_len : natural := slm'length(2);
+    constant col_len : natural := slm'length(1);
+    variable res : matrix(slm'length(1)-1 downto 0, slm'length(2)-1 downto 0);
+  begin
+    for row in 0 to col_len-1 loop
+       for col in 0 to row_len-1 loop
+            res(row, col)  := slv(row*row_len+col);
+       end loop;
+    end loop;
+    return res;
+  end function;
+  
+
+  -- -- inflate std logic vector to m*n matrix 
+  function minflmn(slv : std_logic_vector; col_len : natural; row_len : natural) return matrix is
+    variable res : matrix(col_len-1 downto 0, row_len-1 downto 0);
+  begin
+    for row in 0 to col_len-1 loop
+       for col in 0 to row_len-1 loop
+            res(row, col)  := slv(slv'length-1 - (row*row_len+col));
+       end loop;
+    end loop;
+    return res;
+  end function;
+
+
+end wbgenplus_pkg;