wishbone: wb_onewire_master: added WB slave adapter and xwb_ wrapper, updated copyright info

modules/wishbone/wb_onewire_master/wb_onewire_master.vhd

+------------------------------------------------------------------------------
+-- Title      : Wishbone 1-Wire Master
+-- Project    : General Cores Library (gencores)
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2011-10-04
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Wishbone Dallas/Maxim Semiconductor 1-Wire master.
+-------------------------------------------------------------------------------
+-- 
+-- Based on sockit_owm project Copyright (c) 2010 Iztok Jeras.
+-- http://opencores.org/project,sockit_owm
+--
+-- sockit_owm RTL is licensed under LGPL 3.
+
+-- wb_onewire_master.vhd copyright (c) 2011 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2011-09-18  1.0      twlostow        Created
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.STD_LOGIC_1164.all;
 
 use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
 
 entity wb_onewire_master is
 
   generic(
-    g_num_ports        : integer := 1;
-    g_ow_btp_normal    : string  := "5.0";
-    g_ow_btp_overdrive : string  := "1.0"
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_num_ports           : integer                        := 1;
+    g_ow_btp_normal       : string                         := "5.0";
+    g_ow_btp_overdrive    : string                         := "1.0"
     );  
 
   port (
     clk_sys_i : in std_logic;
     rst_n_i   : in std_logic;
 
-    wb_cyc_i : in std_logic;
-    wb_sel_i : in std_logic_vector(3 downto 0);
-    wb_stb_i : in std_logic;
-    wb_we_i  : in std_logic;
-    wb_adr_i : in std_logic_vector(1 downto 0);
-    wb_dat_i : in std_logic_vector(31 downto 0);
-    wb_dat_o : out std_logic_vector(31 downto 0);
-    wb_ack_o : out std_logic;
-    wb_int_o: out std_logic;
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_adr_i   : in  std_logic_vector(2 downto 0);
+    wb_dat_i   : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_dat_o   : out std_logic_vector(c_wishbone_data_width-1 downto 0);
+    wb_ack_o   : out std_logic;
+    wb_int_o   : out std_logic;
+    wb_stall_o : out std_logic;
 
     owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
     owr_en_o    : out std_logic_vector(g_num_ports -1 downto 0);
@@ -59,13 +89,52 @@ architecture rtl of wb_onewire_master is
   signal bus_wen : std_logic;
   signal bus_ren : std_logic;
   signal rst     : std_logic;
+
+  signal slave_in  : t_wishbone_slave_in;
+  signal slave_out : t_wishbone_slave_out;
+
+  signal adp_out : t_wishbone_master_out;
+  signal adp_in  : t_wishbone_master_in;
+  
 begin  -- rtl
 
-  bus_wen <= wb_cyc_i and wb_stb_i and wb_we_i;
-  bus_ren <= wb_cyc_i and wb_stb_i and not wb_we_i;
+  slave_in.adr(2 downto 0)                          <= wb_adr_i;
+  slave_in.adr(c_wishbone_address_width-1 downto 3) <= (others => '0');
+  slave_in.cyc                                      <= wb_cyc_i;
+  slave_in.stb                                      <= wb_stb_i;
+  slave_in.sel                                      <= wb_sel_i;
+  slave_in.dat                                      <= wb_dat_i;
+  slave_in.we                                       <= wb_we_i;
+
+  wb_int_o   <= slave_out.int;
+  wb_dat_o   <= slave_out.dat;
+  wb_stall_o <= slave_out.stall;
+  wb_ack_o   <= slave_out.ack;
+
+
+  U_Slave_adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i => clk_sys_i,
+      rst_n_i   => rst_n_i,
+
+      slave_i  => slave_in,
+      slave_o  => slave_out,
+      master_i => adp_in,
+      master_o => adp_out);
+
+  
+  bus_wen <= adp_out.cyc and adp_out.stb and adp_out.we;
+  bus_ren <= adp_out.cyc and adp_out.stb and not adp_out.we;
 
-  wb_ack_o <= wb_stb_i and wb_cyc_i;
-  rst      <= not rst_n_i;
+  adp_in.ack <= adp_out.stb and adp_out.cyc;
+  rst        <= not rst_n_i;
 
   Wrapped_1wire : sockit_owm
     generic map (
@@ -77,10 +146,10 @@ begin  -- rtl
       rst     => rst,
       bus_ren => bus_ren,
       bus_wen => bus_wen,
-      bus_adr => wb_adr_i(0 downto 0),
-      bus_wdt => wb_dat_i,
-      bus_rdt => wb_dat_o,
-      bus_irq => wb_int_o,
+      bus_adr => adp_out.adr(0 downto 0),
+      bus_wdt => adp_out.dat,
+      bus_rdt => adp_in.dat,
+      bus_irq => adp_in.int,
       owr_p   => owr_pwren_o,
       owr_e   => owr_en_o,
       owr_i   => owr_i);

modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd

@@ -5,10 +5,11 @@ use work.wishbone_pkg.all;
 
 entity xwb_onewire_master is
   generic(
-    g_interface_mode   : t_wishbone_interface_mode := CLASSIC;
-    g_num_ports        : integer                   := 1;
-    g_ow_btp_normal    : string                    := "5.0";
-    g_ow_btp_overdrive : string                    := "1.0"
+    g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+    g_address_granularity : t_wishbone_address_granularity := WORD;
+    g_num_ports           : integer                        := 1;
+    g_ow_btp_normal       : string                         := "5.0";
+    g_ow_btp_overdrive    : string                         := "1.0"
     );
 
   port(
@@ -32,19 +33,21 @@ architecture rtl of xwb_onewire_master is
 
   component wb_onewire_master
     generic (
-      g_num_ports        : integer;
-      g_ow_btp_normal    : string;
-      g_ow_btp_overdrive : string);
+      g_interface_mode      : t_wishbone_interface_mode      := CLASSIC;
+      g_address_granularity : t_wishbone_address_granularity := WORD;
+      g_num_ports           : integer;
+      g_ow_btp_normal       : string;
+      g_ow_btp_overdrive    : string);
     port (
       clk_sys_i   : in  std_logic;
       rst_n_i     : in  std_logic;
       wb_cyc_i    : in  std_logic;
-      wb_sel_i    : in  std_logic_vector(3 downto 0);
+      wb_sel_i    : in  std_logic_vector(c_wishbone_data_width/8-1 downto 0);
       wb_stb_i    : in  std_logic;
       wb_we_i     : in  std_logic;
-      wb_adr_i    : in  std_logic_vector(1 downto 0);
-      wb_dat_i    : in  std_logic_vector(31 downto 0);
-      wb_dat_o    : out std_logic_vector(31 downto 0);
+      wb_adr_i    : in  std_logic_vector(2 downto 0);
+      wb_dat_i    : in  std_logic_vector(c_wishbone_data_width-1 downto 0);
+      wb_dat_o    : out std_logic_vector(c_wishbone_data_width-1 downto 0);
       wb_ack_o    : out std_logic;
       wb_int_o    : out std_logic;
       owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
@@ -54,26 +57,22 @@ architecture rtl of xwb_onewire_master is
   
 begin  -- rtl
 
-  gen_test_mode : if(g_interface_mode /= CLASSIC) generate
-
-    assert false report "xwb_onewire_master: this module can only work with CLASSIC wishbone interface" severity failure;
-
-  end generate gen_test_mode;
-
-  Wrapped_OW : wb_onewire_master
+  U_Wrapped_1W : wb_onewire_master
     generic map (
-      g_num_ports        => g_num_ports,
-      g_ow_btp_normal    => g_ow_btp_normal,
-      g_ow_btp_overdrive => g_ow_btp_overdrive)
+      g_interface_mode      => g_interface_mode,
+      g_address_granularity => g_address_granularity,
+      g_num_ports           => g_num_ports,
+      g_ow_btp_normal       => g_ow_btp_normal,
+      g_ow_btp_overdrive    => g_ow_btp_overdrive)
     port map (
       clk_sys_i   => clk_sys_i,
       rst_n_i     => rst_n_i,
-      wb_cyc_i    => slave_i.Cyc,
-      wb_sel_i    => slave_i.Sel,
+      wb_cyc_i    => slave_i.cyc,
+      wb_sel_i    => slave_i.sel,
       wb_stb_i    => slave_i.stb,
       wb_we_i     => slave_i.we,
-      wb_adr_i    => slave_i.adr(1 downto 0),
-      wb_dat_i    => slave_i.Dat,
+      wb_adr_i    => slave_i.adr(2 downto 0),
+      wb_dat_i    => slave_i.dat,
       wb_dat_o    => slave_o.dat,
       wb_ack_o    => slave_o.ack,
       wb_int_o    => slave_o.int,
@@ -81,8 +80,7 @@ begin  -- rtl
       owr_en_o    => owr_en_o,
       owr_i       => owr_i);
 
-  slave_o.stall <= '0';
-  slave_o.err   <= '0';
-  slave_o.rty   <= '0';
+  slave_o.err <= '0';
+  slave_o.rty <= '0';
   
 end rtl;