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Commit 29c2dcd0 authored by Mathias Kreider's avatar Mathias Kreider
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fixed bug in round robin

parent 08af7a09
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modules/wishbone/wb_irq/irqm_core.vhd
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...@@ -147,7 +147,7 @@ irq_master_o.we <= '1'; ...@@ -147,7 +147,7 @@ irq_master_o.we <= '1';
if(rst_n_i = '0') then if(rst_n_i = '0') then
idx_robin <= 0; idx_robin <= 0;
else else
if(r_cyc0 = '0' and r_cyc1 = '0') then if(r_cyc0 = '0') then
if(idx_robin = g_channels-1) then if(idx_robin = g_channels-1) then
idx_robin <= 0; idx_robin <= 0;
else else
......
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