gc_frequency_meter: correctly scale output value according to the prescaler

modules/common/gc_frequency_meter.vhd

@@ -11,13 +11,13 @@ entity gc_frequency_meter is
     g_with_internal_timebase : boolean := true;
     g_clk_sys_freq           : integer;
     g_counter_bits           : integer := 32;
-    g_prescaler              : integer := 4);
+    g_prescale_log2          : integer := 4);
 
   port(
     clk_sys_i    : in  std_logic;
     clk_in_i     : in  std_logic;
     rst_n_i      : in  std_logic;
-    pps_p1_i     : in  std_logic;
+    pps_p1_i     : in  std_logic := '0';
     freq_o       : out std_logic_vector(g_counter_bits-1 downto 0);
     freq_valid_o : out std_logic
     );
@@ -33,9 +33,10 @@ architecture behavioral of gc_frequency_meter is
   signal cntr_meas : unsigned(g_counter_bits-1 downto 0);
   signal freq_reg  : std_logic_vector(g_counter_bits-1 downto 0);
 
-  signal prescaler_cnt : unsigned(3 downto 0);
+  signal prescaler_cnt : unsigned(g_prescale_log2-2 downto 0);
   signal prescaled_in  : std_logic;
-  signal tick : std_logic;
+  signal tick          : std_logic;
+  signal freq_valid_d  : std_logic;
 begin
 
   gen_internal_timebase : if(g_with_internal_timebase = true) generate
@@ -66,10 +67,10 @@ begin
 
     U_Sync_Gate : gc_sync_ffs
       port map (
-        clk_i  => clk_sys_i,
-        rst_n_i   => rst_n_i,
-        data_i     => pps_p1_i,
-        ppulse_o     => gate_pulse_synced);
+        clk_i    => clk_sys_i,
+        rst_n_i  => rst_n_i,
+        data_i   => pps_p1_i,
+        ppulse_o => gate_pulse_synced);
   end generate gen_external_timebase;
 
 
@@ -79,7 +80,7 @@ begin
       prescaler_cnt <= (others => '0');
       prescaled_in  <= '0';
     elsif rising_edge(clk_in_i) then
-      if(prescaler_cnt = g_prescaler-1) then
+      if(not prescaler_cnt = 0) then
         prescaler_cnt <= (others => '0');
         prescaled_in  <= not prescaled_in;
       else
@@ -91,28 +92,32 @@ begin
 
   U_Sample_Clock : gc_sync_ffs
     port map (
-      clk_i  => clk_sys_i,
-      rst_n_i   => rst_n_i,
-      data_i     => prescaled_in,
-      ppulse_o     => tick);
-  
+      clk_i    => clk_sys_i,
+      rst_n_i  => rst_n_i,
+      data_i   => prescaled_in,
+      ppulse_o => tick);
+
   p_freq_counter : process (clk_sys_i, rst_n_i)
   begin
     if rst_n_i = '0' then               -- asynchronous reset (active low)
-      cntr_meas <= (others => '0');
-      freq_reg  <= (others => '0');
-    elsif rising_edge(clk_in_i) then
+      cntr_meas    <= (others => '0');
+      freq_reg     <= (others => '0');
+      freq_valid_o <= '0';
+      freq_valid_d <= '0';
+    elsif rising_edge(clk_sys_i) then
 
       if(gate_pulse_synced = '1') then
-        freq_reg  <= std_logic_vector(cntr_meas);
-        cntr_meas <= (others => '0');
+        freq_reg     <= std_logic_vector(cntr_meas);
+        freq_valid_o <= freq_valid_d;
+        freq_valid_d <= '1';
+        cntr_meas    <= (others => '0');
       elsif (tick = '1') then
         cntr_meas <= cntr_meas + 1;
       end if;
     end if;
   end process p_freq_counter;
 
-  freq_o <= freq_reg;
+  freq_o <= std_logic_vector(unsigned(freq_reg) sll g_prescale_log2);
 end behavioral;