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kostas_dev
3051df4c
·
Final update to README in AXI/ tests
·
Jan 13, 2023
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tom-mr-new-wishbone-cores
8da5b724
·
Updated README.md with addition of the new WB cores
·
Dec 15, 2022
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tom-mr-dsp-cores
d49f61cb
·
Updated README.md with info about the DSP cores
·
Dec 15, 2022
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tom-mr-axi-package-fixes
a1d90f23
·
axi4_pkg: Added missing AxPROT fields + fixed WSTRB length in AXI4-Full record typedefs
·
Dec 15, 2022
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tom-mr-sv-sim-rework
dd3a22e8
·
sim: updated license headers
·
Dec 15, 2022
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tom-ucc-virtex5
e4bee0f0
·
xwb_lm32_mcs: implement firmware preloading using generic_dpram_split
·
Dec 14, 2022
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gsi_master_get_back_on_track
a637d457
·
common: add gc_dec_8b10b and gc_enc_8b10b to Manifest.py
·
Dec 01, 2022
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npittet-pi-reg-changes
799c7394
·
dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning),...
·
Aug 02, 2022
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altera_works
7f6c088b
·
conditional manifests for xilinx devices
·
Jun 22, 2022
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wb_axi4lite_bridge_fix
c5599a5a
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Fixed an issue where the "RESPONSE_READ" was skipped.
·
May 12, 2022
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tom-afcz-v2
8170acea
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genrams: KEEP attribute for FIFO resets to facilitate constraining
·
Feb 03, 2022
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gsi_master_get_back_on_track_2022
07b86875
·
merging: solved conflicts
·
Jan 10, 2022
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esrf_v1.1.1
f7578270
·
apply xilinx recommendation for clock domain crossing and sync reset
·
Oct 26, 2021
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tom-rf
dfdb1574
·
wb_fine_pulse_gen: support for configurable pulse width. INTERFACE CHANGED.
·
May 11, 2021
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vivado-2019.2
b75fe3d5
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gc_frequency_meter: DO NOT MERGE, temporary fix to make buggy vivado hierarchy solver happy
·
May 06, 2021
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sync_reset_state
cb09c893
·
Add configurable reset state for sync/edge_detect IP
·
Apr 15, 2021
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peter_210106_spec7
55d2e8cc
·
added processing_system_pcie.bd
·
Jan 06, 2021
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tom-dec11
ed011735
·
wb_xc7_fw_update: keep STARTUP primitive outside the core
·
Dec 11, 2020
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peter_201007
012b58c6
·
added processing_system_pcie.bd
·
Oct 07, 2020
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pascal_201006
7498609f
·
renamed pci to pcie, moved to bd format
·
Oct 07, 2020
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