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\section*{Revision history}

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{
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  \multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
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  03-03-2014 & 0.01 & First draft \\
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\section*{List of Abbreviations}
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FF & Flip-Flop \\
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\section{Introduction}
\label{sec:intro}

This document presents the \textit{gc\_glitch\_filt} component, a modular glitch
filter open-hardware~\cite{ohwr} design for FPGA or ASIC implementation. It is
implemented as one short VHDL file which can be found under the following folder
of the \textit{general-cores} repository~\cite{gencores-ohwr}:

\begin{itemize}
\item \textit{modules/common/}
\end{itemize}

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\section{Instantiation}
\label{sec:instantiation}

Table~\ref{tbl:ports} shows the instantiation template for the \textit{gc\_glitch\_filt}
component. It can be directly instantiated in a VHDL or Verilog design.

The data to be filtered should be connected to the \textit{dat\_i} input. Note that
the data is not synchronized internally to the \textit{clk\_i} signal, if metastability
is a concern, a synchronization chain should be provided outside the component.

The deglitched data is presented at the \textit{dat\_o} output a number of \textit{g\_len+1}
clock cycles later.

\begin{table}[h]
  \caption{Ports and generics of \textit{gc\_i2c\_slave} module}
  \label{tbl:ports}
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  {
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      \multicolumn{1}{c}{\textbf{Name}} & \multicolumn{1}{c}{\textbf{Description}} \\
      \hline
      g\_len & Glitch filter length generic (in \textit{clk\_i} cycles) \newline
               1 -- glitches narrower than 1 \textit{clk\_i} cycle are filtered \newline
               2 -- glitches narrower than 2 \textit{clk\_i} cycles are filtered \newline
               etc.\\
      \hline
      clk\_i & Clock input \\
      rst\_n\_i & Active-low reset input \\
      dat\_i & Data input (should be synchronous to \textit{clk\_i})\\
      dat\_o & Deglitched data output (synchronous to \textit{clk\_i}) \\
      \hline
    \end{tabular}
  }
\end{table}

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\section{Implementation and operation}

Figure~\ref{fig:implem} shows the implementation of the \textit{gc\_glitch\_filt}
block.

\begin{figure}[h]
  \centerline{\includegraphics[width=\textwidth]{fig/implem}}
  \caption{Implementation of the \textit{gc\_glitch\_filt} block}
  \label{fig:implem}
\end{figure}

The block's operation is very simple and can be summarized as follows. At synthesis
time, \textit{g\_len} FFs are generated. If the \textit{dat\_i} is stable for a number
of \textit{g\_len} cycles, all FFs in the deglitching stage have the same value,
and the \textit{dat\_o} output changes to reflect the state of \textit{dat\_i}.
Should a glitch occur at any time on the \textit{dat\_i} signal, it is filtered
by the AND (or NAND) gate at the output.

All the FFs are cleared ('0') on reset.

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