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468b5637
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Merge branch 'tg-axi4' into 'master'
·
Nov 26, 2024
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gsi_fallout_release_quartus_23_1_1
9467ead2
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pcie_altera: fix scu2/3 and vetar2a
·
Nov 14, 2024
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56-axi4_pkg-incorrect-width
c8bb6498
·
Update .ohwr.yaml
·
Oct 02, 2024
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gsi_fallout_release
fff16157
·
altera/ftm4: fix pcie instantiation errors
·
Jun 18, 2024
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harvey-dev
8cdc66fd
·
increased max number of i2c slave interfaces in mux
·
Mar 19, 2024
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wrs-v4-dev
8cdc66fd
·
increased max number of i2c slave interfaces in mux
·
Mar 19, 2024
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gsi_master_get_back_on_track_2024
e8e3a4fc
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merge master into gsi_master_get_back_on_trask_2024
·
Feb 28, 2024
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52-possible_fix_in_wb_uart_rx_fifo
f3f78ce9
·
RTL change in wb_uart in the way we read the RX FIFO
·
Jan 23, 2024
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51-inferred_async_fifo_dual_reset-spurious-pulse-on-almost_full_int-after-reset
91ebb21c
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fix missing statement that would pulse almost_full_int in simulation
·
Jan 22, 2024
!59
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tom-wrpcv5-dev
2ae8ad3d
·
wb_fine_pulse_gen: work in progress on switching between pulse/continuous clock mode
·
Jan 15, 2024
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47-revert-version-of-wb_uart
c1277ee6
·
Working version of wb_uart used in ProFip
·
Dec 15, 2023
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46-demo_vunit_ghdl_testbench
17ac0f43
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First draft of the demo of gc_edge_detect TB using VUnit
·
Dec 13, 2023
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45-addition-of-a-register-in-wb_uart-to-show-the-endianess
874afe5c
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Addition of a register to check the endianess in wb_uart
·
Dec 08, 2023
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proposed_master
protected
3f28d459
·
Merge branch 'fix-mpsoc-int-gen' into 'proposed_master'
·
Oct 10, 2023
!29
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cordic_changes
c51d2c10
·
fixing cordic doc
·
Aug 11, 2023
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hm-wrslj-v6
0352a53d
·
add dac_sel for gc_serial_dac.vhd
·
Jun 11, 2023
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sowarzan-rf
badc697f
·
modules/genrams/generic/ replace log2 function by
·
May 15, 2023
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tom-proposed-master
e38b5280
·
wb_uart: testbench with regression cases against different combinations of...
·
Mar 10, 2023
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tom-uart-fixes
e38b5280
·
wb_uart: testbench with regression cases against different combinations of...
·
Mar 10, 2023
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wrpc-v4.2-damc-fmc2zup
ebfcc751
·
xwb_axi4_bridge: fix issues with the AXI4 side
·
Jan 30, 2023
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