This is a testbench to verify the xwb_clock_bridge core. As input, this test has random values, with random seed with OSVVM methodology. The behavior of this testbench is very similar to the one in the RTL core. For simulation reasons, it contains also the 2 FIFOs that the core uses, mostly because the write and read enable signals are useful for the test. There are two assertions processes, which compare always the output of the RTL (master_o and slave_o) with the output of the testbench (output of second FIFO and data stored in an array).

As for the generics, `g_slave_port_wb_mode` and `g_master_port_wb_mode` are `PIPELINED` and they can not be changed. The only generic that can be changed is the `g_size`, which is the depth of FIFOs and for simulation reasons, it is preferable not to have a high number.
