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Wesley W. Terpstra authored
Each clock domain needs a separate reset line. However, one cannot reset only a single domain---that could cause inconsistency at clock crossing boundaries. This change splits reset lines per clock domain and centralizes generation.
1f7fae25
Manifest.py 531 B
files = [ "gencores_pkg.vhd",
"gc_crc_gen.vhd",
"gc_moving_average.vhd",
"gc_extend_pulse.vhd",
"gc_delay_gen.vhd",
"gc_dual_pi_controller.vhd",
"gc_reset.vhd",
"gc_serial_dac.vhd",
"gc_sync_ffs.vhd",
"gc_arbitrated_mux.vhd",
"gc_pulse_synchronizer.vhd",
"gc_frequency_meter.vhd",
"gc_dual_clock_ram.vhd",
"gc_wfifo.vhd"];