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-------------------------------------------------------------------------------
-- Title : Pulse width extender
-- Project : General Cores library
-------------------------------------------------------------------------------
-- File : gc_extend_pulse.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2009-09-01
-- Last update: 2011-04-29
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Description:
-- Synchronous pulse extender. Generates a pulse of programmable width upon
-- detection of a rising edge in the input.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009-2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2009-09-01 0.9 twlostow Created
-- 2011-04-18 1.0 twlostow Added comments & header
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.gencores_pkg.all;
entity gc_extend_pulse is
generic (
-- output pulse width in clk_i cycles
g_width : natural := 1000
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- input pulse (synchronou to clk_i)
pulse_i : in std_logic;
-- extended output pulse
extended_o : out std_logic);
end gc_extend_pulse;
architecture rtl of gc_extend_pulse is
signal cntr : unsigned(31 downto 0);
begin -- rtl
extend : process (clk_i, rst_n_i)
begin -- process extend
if rst_n_i = '0' then -- asynchronous reset (active low)
extended_o <= '0';
cntr <= (others => '0');
elsif clk_i'event and clk_i = '1' then -- rising clock edge
if(pulse_i = '1') then
extended_o <= '1';
cntr <= to_unsigned(g_width, cntr'length);
elsif cntr /= to_unsigned(0, cntr'length) then
cntr <= cntr - 1;
else
extended_o <= '0';
end if;
end if;
end process extend;
end rtl;