sys_top_dma.vhd: clear fifo errors and max at the start of a transfer

b4d09c9e · Tristan Gingold · Maciej Lipinski · 81d2b6d6 · b4d09c9e
Commit b4d09c9e authored Nov 24, 2021 by Tristan Gingold Committed by Maciej Lipinski Nov 26, 2021
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Showing with 10 additions and 5 deletions

sys_top_dma.vhd hdl/rtl/sys/sys_top_dma.vhd +10 -5

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--- a/hdl/rtl/sys/sys_top_dma.vhd
+++ b/hdl/rtl/sys/sys_top_dma.vhd
@@ -159,11 +159,16 @@ begin
        samples_valid_d <= samples_valid_i;

        --  Fifo stats
-        if fifo_full = '1' and samples_valid_i = '1' and fifo_errs /= x"ff" then
-          fifo_errs <= fifo_errs + 1;
-        end if;
-        if unsigned(wr_count) > fifo_max then
-          fifo_max <= unsigned(wr_count);
+        if samples_start_i = '1' then
+          fifo_errs <= (others => '0');
+          fifo_max <= (others => '0');
+        else
+          if fifo_full = '1' and samples_valid_i = '1' and fifo_errs /= x"ff" then
+            fifo_errs <= fifo_errs + 1;
+          end if;
+          if unsigned(wr_count) > fifo_max then
+            fifo_max <= unsigned(wr_count);
+          end if;
        end if;
      end if;