sys_top_dma.vhd: clear fifo errors and max at the start of a transfer

b4d09c9e · Tristan Gingold · Maciej Lipinski · 81d2b6d6 · b4d09c9e
Commit b4d09c9e authored Nov 24, 2021 by Tristan Gingold Committed by Maciej Lipinski Nov 26, 2021
Show whitespace changes
Inline Side-by-side

Showing with 10 additions and 5 deletions

sys_top_dma.vhd hdl/rtl/sys/sys_top_dma.vhd +10 -5

No files found.
--- a/hdl/rtl/sys/sys_top_dma.vhd
+++ b/hdl/rtl/sys/sys_top_dma.vhd
@@ -159,6 +159,10 @@ begin
        samples_valid_d <= samples_valid_i;

        --  Fifo stats
+        if samples_start_i = '1' then
+          fifo_errs <= (others => '0');
+          fifo_max <= (others => '0');
+        else
          if fifo_full = '1' and samples_valid_i = '1' and fifo_errs /= x"ff" then
            fifo_errs <= fifo_errs + 1;
          end if;
@@ -166,6 +170,7 @@ begin
            fifo_max <= unsigned(wr_count);
          end if;
        end if;
+      end if;

      -- Linearize the data for the fifo.
      for i in 0 to 3 loop