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FSI Data Acquisition Path Gateware and Software
Commit 81d2b6d6 authored by Tristan Gingold's avatar Tristan Gingold Committed by Maciej Lipinski
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sys: add dma_done register field (not tested)

parent 35469023
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Showing with 87 additions and 15 deletions
hdl/rtl/sys/diot_sys_top.vhd
View file @ 81d2b6d6
......@@ -283,6 +283,8 @@ architecture arch of diot_sys_top is
signal tfr_fifo_errs_0, tfr_fifo_errs_1 : std_logic_vector(7 downto 0);
signal tfr_fifo_max_0, tfr_fifo_max_1 : std_logic_vector(7 downto 0);
signal tfr_axi_errs_0, tfr_axi_errs_1 : std_logic_vector(3 downto 0);
signal dma_empty_0, dma_empty_1 : std_logic;
signal dma_done : std_logic;
signal patterns_sel, patterns_sel_in : std_logic;
......@@ -666,6 +668,7 @@ begin
rready => s_rready_csr,
rdata => s_rdata_csr,
rresp => s_rresp_csr,
status_dma_done_i => dma_done,
status_sampling_i => sampling,
status_transfer_i => status_transfer,
status_ready_i => periph_ready,
......@@ -830,6 +833,7 @@ begin
samples_valid_i => samples_valid,
samples_start_i => trigger_in,
dma_start_address_i => tfr_address_0,
dma_fifo_empty_o => dma_empty_0,
dma_fifo_max_o => tfr_fifo_max_0,
dma_fifo_errs_o => tfr_fifo_errs_0,
dma_axi_errs_o => tfr_axi_errs_0,
......@@ -863,6 +867,7 @@ begin
samples_valid_i => samples_valid,
samples_start_i => trigger_in,
dma_start_address_i => tfr_address_1,
dma_fifo_empty_o => dma_empty_1,
dma_fifo_max_o => tfr_fifo_max_1,
dma_fifo_errs_o => tfr_fifo_errs_1,
dma_axi_errs_o => tfr_axi_errs_1,
......@@ -886,6 +891,36 @@ begin
m_axi_dat_bready => m_axi_dat1_bready
);
process (clk_100m)
variable armed, dma_done_0, dma_done_1 : boolean;
begin
if rising_edge(clk_100m) then
dma_done <= '0';
if rst_n = '0' then
armed := false;
else
if not armed then
if sampling = '1' then
armed := true;
dma_done_0 := false;
dma_done_1 := false;
end if;
else
if dma_empty_0 = '1' then
dma_done_0 := true;
end if;
if dma_empty_1 = '1' then
dma_done_1 := true;
end if;
if dma_done_0 and dma_done_1 then
armed := false;
dma_done <= '1';
end if;
end if;
end if;
end if;
end process;
-- inst_ila: ila_0
-- port map (
-- clk => clk_300m,
......
hdl/rtl/sys/sys_top_dma.vhd
View file @ 81d2b6d6
......@@ -22,6 +22,7 @@ entity sys_top_dma is
-- From the register maps (use clk_100m_i)
dma_start_address_i : std_logic_vector(31 downto 0);
dma_fifo_empty_o : out std_logic;
dma_fifo_max_o : out std_logic_vector(7 downto 0);
dma_fifo_errs_o : out std_logic_vector(7 downto 0);
dma_axi_errs_o : out std_logic_vector(3 downto 0);
......@@ -114,7 +115,7 @@ begin
g_with_rd_almost_empty => False,
g_with_rd_almost_full => False,
g_with_rd_count => False,
g_with_wr_empty => False,
g_with_wr_empty => True,
g_with_wr_full => True,
g_with_wr_almost_empty => False,
g_with_wr_almost_full => False,
......@@ -127,7 +128,7 @@ begin
clk_wr_i => clk_100m_i,
d_i => fifo_din,
we_i => fifo_we,
wr_empty_o => open,
wr_empty_o => dma_fifo_empty_o,
wr_full_o => fifo_full,
wr_almost_empty_o => open,
wr_almost_full_o => open,
......
hdl/rtl/sys/sys_top_sub_regs.cheby
View file @ 81d2b6d6
......@@ -14,21 +14,33 @@ memory-map:
- reg:
name: status
width: 32
access: ro
access: rw
children:
- field:
name: dma_done
description: Set at end of DMA transfer, write 1 to clear
range: 3
x-hdl:
type: or-clr
- field:
name: sampling
description: Peripheral boards are sending samples
comment: When set, commands or values cannot be transmitted
range: 2
x-hdl:
type: wire
- field:
name: ready
description: All peripheral boards are ready
range: 1
x-hdl:
type: wire
- field:
name: transfer
description: Data transfer (DMA) in progress
range: 0
x-hdl:
type: wire
- reg:
name: control
width: 32
......
hdl/rtl/sys/sys_top_sub_regs.vhd
View file @ 81d2b6d6
-- Do not edit. Generated on Mon Sep 13 08:39:58 2021 by tgingold
-- Do not edit. Generated on Tue Nov 23 09:55:22 2021 by tgingold
-- With Cheby 1.5.dev0 and these options:
-- --gen-hdl=sys_top_sub_regs.vhd -i sys_top_sub_regs.cheby
......@@ -32,12 +32,17 @@ entity sys_top_sub_reg is
rresp : out std_logic_vector(1 downto 0);
-- REG status
-- Set at end of DMA transfer, write 1 to clear
status_dma_done_i : in std_logic;
-- When set, commands or values cannot be transmitted
status_sampling_i : in std_logic;
status_sampling_o : out std_logic;
-- All peripheral boards are ready
status_ready_i : in std_logic;
status_ready_o : out std_logic;
-- Data transfer (DMA) in progress
status_transfer_i : in std_logic;
status_transfer_o : out std_logic;
-- REG control
-- Sampling software trigger
......@@ -191,7 +196,6 @@ architecture syn of sys_top_sub_reg is
signal wr_ack : std_logic;
signal wr_addr : std_logic_vector(7 downto 2);
signal wr_data : std_logic_vector(31 downto 0);
signal wr_strb : std_logic_vector(3 downto 0);
signal axi_awset : std_logic;
signal axi_wset : std_logic;
signal axi_wdone : std_logic;
......@@ -201,6 +205,9 @@ architecture syn of sys_top_sub_reg is
signal rd_data : std_logic_vector(31 downto 0);
signal axi_arset : std_logic;
signal axi_rdone : std_logic;
signal status_dma_done_reg : std_logic;
signal status_wreq : std_logic;
signal status_wack : std_logic;
signal control_sw_trig_reg : std_logic;
signal control_prbs_reg : std_logic;
signal control_wreq : std_logic;
......@@ -232,7 +239,6 @@ architecture syn of sys_top_sub_reg is
signal cmd_ctrl_exec_reg : std_logic;
signal cmd_ctrl_wreq : std_logic;
signal cmd_ctrl_wack : std_logic;
signal cmd_status_wreq : std_logic;
signal stat_sel_ch_reg : std_logic_vector(3 downto 0);
signal stat_sel_board_reg : std_logic_vector(2 downto 0);
signal stat_sel_delay_reg : std_logic;
......@@ -251,7 +257,6 @@ architecture syn of sys_top_sub_reg is
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(7 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- AW, W and B channels
......@@ -274,7 +279,6 @@ begin
end if;
if wvalid = '1' and axi_wset = '0' then
wr_data <= wdata;
wr_strb <= wstrb;
axi_wset <= '1';
wr_req <= axi_awset or awvalid;
end if;
......@@ -333,7 +337,6 @@ begin
wr_req_d0 <= wr_req;
wr_adr_d0 <= wr_addr;
wr_dat_d0 <= wr_data;
wr_sel_d0 <= wr_strb;
end if;
end if;
end process;
......@@ -341,6 +344,24 @@ begin
-- Register ident
-- Register status
status_sampling_o <= wr_dat_d0(2);
status_ready_o <= wr_dat_d0(1);
status_transfer_o <= wr_dat_d0(0);
process (aclk) begin
if rising_edge(aclk) then
if areset_n = '0' then
status_dma_done_reg <= '0';
status_wack <= '0';
else
if status_wreq = '1' then
status_dma_done_reg <= status_dma_done_i or (status_dma_done_reg and not wr_dat_d0(3));
else
status_dma_done_reg <= status_dma_done_i or status_dma_done_reg;
end if;
status_wack <= status_wreq;
end if;
end if;
end process;
-- Register control
control_sw_trig_o <= control_sw_trig_reg;
......@@ -599,7 +620,8 @@ begin
-- Register delay_cntvalue
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, control_wack, config_wack, length_wack, configs_0_address_wack, configs_1_address_wack, cmd_boards_wack, cmd_value_wack, cmd_ctrl_wack, stat_sel_wack, delay_ctrl_wack) begin
process (wr_adr_d0, wr_req_d0, status_wack, control_wack, config_wack, length_wack, configs_0_address_wack, configs_1_address_wack, cmd_boards_wack, cmd_value_wack, cmd_ctrl_wack, stat_sel_wack, delay_ctrl_wack) begin
status_wreq <= '0';
control_wreq <= '0';
config_wreq <= '0';
length_wreq <= '0';
......@@ -608,7 +630,6 @@ begin
cmd_boards_wreq <= '0';
cmd_value_wreq <= '0';
cmd_ctrl_wreq <= '0';
cmd_status_wreq <= '0';
stat_sel_wreq <= '0';
delay_ctrl_wreq <= '0';
case wr_adr_d0(7 downto 3) is
......@@ -619,7 +640,8 @@ begin
wr_ack <= wr_req_d0;
when "1" =>
-- Reg status
wr_ack <= wr_req_d0;
status_wreq <= wr_req_d0;
wr_ack <= status_wack;
when others =>
wr_ack <= wr_req_d0;
end case;
......@@ -712,7 +734,6 @@ begin
wr_ack <= cmd_ctrl_wack;
when "1" =>
-- Reg cmd_status
cmd_status_wreq <= wr_req_d0;
wr_ack <= wr_req_d0;
when others =>
wr_ack <= wr_req_d0;
......@@ -818,7 +839,7 @@ begin
end process;
-- Process for read requests.
process (rd_addr, rd_req, status_transfer_i, status_ready_i, status_sampling_i, control_prbs_reg, config_trig_en_reg, config_patterns_reg, config_rst_n_reg, config_clk_sel_reg, config_periph_off_reg, length_reg, configs_0_address_reg, configs_0_cur_address_i, configs_0_status_axi_i, configs_0_status_fifo_max_i, configs_0_status_fifo_errs_i, configs_1_address_reg, configs_1_cur_address_i, configs_1_status_axi_i, configs_1_status_fifo_max_i, configs_1_status_fifo_errs_i, periph_stat1_inp_i, periph_stat1_triggers_i, periph_stat1_spi_busy_i, periph_stat2_rx_locked_i, periph_stat2_adc_locked_i, periph_stat2_sys_locked_i, periph_stat2_fsi_ready_i, cmd_boards_sel_reg, cmd_value_reg, cmd_status_err_i, cmd_status_done_i, cmd_reply_0_value_i, cmd_reply_1_value_i, cmd_reply_2_value_i, cmd_reply_3_value_i, cmd_reply_4_value_i, cmd_reply_5_value_i, cmd_reply_6_value_i, cmd_reply_7_value_i, stat_sel_ch_reg, stat_sel_board_reg, stat_sel_delay_reg, stat_sel_branch_reg, stat_clock_i, stat_bit_lock_i, stat_byte_lock_i, stat_prbs_i, delay_ctrl_vtc_en_reg, delay_ctrl_freeze_reg, delay_cntvalue_i) begin
process (rd_addr, rd_req, status_transfer_i, status_ready_i, status_sampling_i, status_dma_done_reg, control_prbs_reg, config_trig_en_reg, config_patterns_reg, config_rst_n_reg, config_clk_sel_reg, config_periph_off_reg, length_reg, configs_0_address_reg, configs_0_cur_address_i, configs_0_status_axi_i, configs_0_status_fifo_max_i, configs_0_status_fifo_errs_i, configs_1_address_reg, configs_1_cur_address_i, configs_1_status_axi_i, configs_1_status_fifo_max_i, configs_1_status_fifo_errs_i, periph_stat1_inp_i, periph_stat1_triggers_i, periph_stat1_spi_busy_i, periph_stat2_rx_locked_i, periph_stat2_adc_locked_i, periph_stat2_sys_locked_i, periph_stat2_fsi_ready_i, cmd_boards_sel_reg, cmd_value_reg, cmd_status_err_i, cmd_status_done_i, cmd_reply_0_value_i, cmd_reply_1_value_i, cmd_reply_2_value_i, cmd_reply_3_value_i, cmd_reply_4_value_i, cmd_reply_5_value_i, cmd_reply_6_value_i, cmd_reply_7_value_i, stat_sel_ch_reg, stat_sel_board_reg, stat_sel_delay_reg, stat_sel_branch_reg, stat_clock_i, stat_bit_lock_i, stat_byte_lock_i, stat_prbs_i, delay_ctrl_vtc_en_reg, delay_ctrl_freeze_reg, delay_cntvalue_i) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
case rd_addr(7 downto 3) is
......@@ -834,7 +855,8 @@ begin
rd_dat_d0(0) <= status_transfer_i;
rd_dat_d0(1) <= status_ready_i;
rd_dat_d0(2) <= status_sampling_i;
rd_dat_d0(31 downto 3) <= (others => '0');
rd_dat_d0(3) <= status_dma_done_reg;
rd_dat_d0(31 downto 4) <= (others => '0');
when others =>
rd_ack_d0 <= rd_req;
end case;
......
hdl/tb/diot_sys_tb/sys_top_sub_regs.sv
View file @ 81d2b6d6
......@@ -3,6 +3,8 @@ package sys_top_sub_reg_Consts;
localparam ADDR_SYS_TOP_SUB_REG_IDENT = 'h0;
localparam SYS_TOP_SUB_REG_IDENT_PRESET = 32'h46534932;
localparam ADDR_SYS_TOP_SUB_REG_STATUS = 'h4;
localparam SYS_TOP_SUB_REG_STATUS_DMA_DONE_OFFSET = 3;
localparam SYS_TOP_SUB_REG_STATUS_DMA_DONE = 32'h8;
localparam SYS_TOP_SUB_REG_STATUS_SAMPLING_OFFSET = 2;
localparam SYS_TOP_SUB_REG_STATUS_SAMPLING = 32'h4;
localparam SYS_TOP_SUB_REG_STATUS_READY_OFFSET = 1;
......
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