* Dequeue operations as they arrive
  * Support variable WB bus size
  * Don't push zeros to client

  * Had to re-order initialization; pci_device_enable must precede pci_enable_msi
  * Must enable master mode on the device to receive MSIs and/or bus master
  * Report the address/data from the bridge

Wesley W. Terpstra authored 12 years ago and Alessandro Rubini committed 12 years ago

This never appeared until now because it only failed if two records appeared at once.

Wesley W. Terpstra authored 12 years ago and Alessandro Rubini committed 12 years ago

Debugging with bad information sucks!

Wesley W. Terpstra authored 12 years ago and Alessandro Rubini committed 12 years ago

  Don't overflow the buffer! Compare the index for overflow not the position.
  Read/write of 0 returns 0 even when non-blocking.

Wesley W. Terpstra authored 12 years ago and Alessandro Rubini committed 12 years ago

This would break the read (non-posted) and write (posted) ordering that Wishbone depends on.

Wesley W. Terpstra authored 12 years ago and Alessandro Rubini committed 12 years ago

Currently hardcode SDWB address as hardware does not support it.

Wesley W. Terpstra authored 12 years ago and Alessandro Rubini committed 12 years ago

Fixed bugs in kernel etherbone:
  record_len was shadowed by redeclation
  wrote maximum of possible bytes instead of minimum
  added non-blocking IO support

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>