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FPGA Configuration Space
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3b0d39a8
Commit
3b0d39a8
authored
12 years ago
by
Alessandro Rubini
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docs/Makefile: compile all .tex present in the dir
parent
6d2a679d
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docs/specification/Makefile
+8
-7
8 additions, 7 deletions
docs/specification/Makefile
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8 additions
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7 deletions
docs/specification/Makefile
+
8
−
7
View file @
3b0d39a8
FILE
=
proposal
INPUT
=
$(
wildcard
*
.tex
)
ALL
=
$(
INPUT:.tex
=
.pdf
)
all
:
$(
FILE).pdf
all
:
$(
ALL)
$(FILE).pdf
:
$(FILE)
.tex sdb-h.expand
latex
$
(
FILE
)
.tex
latex
$
(
FILE
)
.tex
dvipdfm
$
(
FILE
)
.dvi
%.pdf
:
%
.tex sdb-h.expand
latex
$
*
.tex
latex
$
*
.tex
dvipdfm
$
*
.dvi
clean
:
rm
-rf
*
.aux
*
.dvi
*
.log
*
.pdf
*
.toc
*
.lot
*
.lof
sdb-h.expand
:
sdb.h
expand
-8
$^
>
$@
\ No newline at end of file
expand
-8
$^
>
$@
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