working wishbone output! (8feb4fc7) · Commits · Projects / FPGA Configuration Space · GitLab

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8feb4fc7

Commit 8feb4fc7 authored 12 years ago by

Wesley W. Terpstra

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working wishbone output!

parent 1398bcdf

No related merge requests found

Changes 6

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hdl/altera_pcie.vhd 7 additions, 7 deletions

hdl/altera_pcie.vhd
hdl/altera_pcie_core.vhd 2 additions, 10 deletions

hdl/altera_pcie_core.vhd
hdl/pcie_tlp.vhd 251 additions, 0 deletions

hdl/pcie_tlp.vhd
hdl/pcie_wb.qsf 333 additions, 619 deletions

hdl/pcie_wb.qsf
hdl/pcie_wb.vhd 30 additions, 10 deletions

hdl/pcie_wb.vhd
hdl/pcie_wb_pkg.vhd 18 additions, 0 deletions

hdl/pcie_wb_pkg.vhd

with 641 additions and 646 deletions

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