Skip to content
Snippets Groups Projects
Commit 8feb4fc7 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
Browse files

working wishbone output!

parent 1398bcdf
Branches
Tags
No related merge requests found
Expand all Hide whitespace changes
Inline Side-by-side
hdl/altera_pcie.vhd
+ 7
− 7
View file @ 8feb4fc7
......@@ -1269,7 +1269,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pci_maximum_burst_size_a2p" value="128" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_maximum_pending_read_transactions_a2p" value="8" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_non_pref_av_master_port" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_not_target_only_port" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_not_target_only_port" value="false" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_pref_av_master_port" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_reqn_gntn_pins" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pci_single_clock" value="false" type="STRING" enable="1" />
......@@ -1283,21 +1283,21 @@ end europa;
-- Retrieval info: <PRIVATE name = "p_pcie_altgx_keyParameters_used" value="{p_pcie_enable_hip=1, p_pcie_number_of_lanes=x4, p_pcie_phy=Arria II GX, p_pcie_rate=Gen1 (2.5 Gbps), p_pcie_txrx_clock=100 MHz}" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_app_signal_interface" value="AvalonST" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_avalon_mm_lite" value="0" type="INTEGER" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_0" value="256 Bytes - 8 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_1" value="64 MBytes - 26 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_2" value="64 MBytes - 26 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_0" value="128 Bytes - 7 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_1" value="16 MBytes - 24 bits" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_2" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_3" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_4" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_size_bar_5" value="N/A" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_0" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_1" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_2" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_2" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_3" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_4" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_type_bar_5" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_0" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_1" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_2" value="1" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_2" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_3" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_4" value="0" type="BOOLEAN" enable="1" />
-- Retrieval info: <PRIVATE name = "p_pcie_bar_used_bar_5" value="0" type="BOOLEAN" enable="1" />
......@@ -1478,7 +1478,7 @@ end europa;
-- Retrieval info: <PRIVATE name = "uiFixedTable" value="true" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar0Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar1Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar2Type" value="32-bit Non-Prefetchable Memory" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar2Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar3Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar4Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
-- Retrieval info: <PRIVATE name = "uiPCIBar5Type" value="Disable this and all higher BARs" type="STRING" enable="1" />
......
hdl/altera_pcie_core.vhd
+ 2
− 10
View file @ 8feb4fc7
......@@ -301,10 +301,6 @@ ARCHITECTURE SYN OF altera_pcie_core IS
bar1_64bit_mem_space : STRING;
bar1_prefetchable : STRING;
bar1_size_mask : NATURAL;
bar2_io_space : STRING;
bar2_64bit_mem_space : STRING;
bar2_prefetchable : STRING;
bar2_size_mask : NATURAL;
enable_ecrc_check : STRING;
enable_ecrc_gen : STRING;
enable_l1_aspm : STRING;
......@@ -766,15 +762,11 @@ BEGIN
bar0_io_space => "false",
bar0_64bit_mem_space => "false",
bar0_prefetchable => "false",
bar0_size_mask => 8,
bar0_size_mask => 7,
bar1_io_space => "false",
bar1_64bit_mem_space => "false",
bar1_prefetchable => "false",
bar1_size_mask => 26,
bar2_io_space => "false",
bar2_64bit_mem_space => "false",
bar2_prefetchable => "false",
bar2_size_mask => 26,
bar1_size_mask => 24,
enable_ecrc_check => "false",
enable_ecrc_gen => "false",
enable_l1_aspm => "false",
......
hdl/pcie_tlp.vhd 0 → 100644
+ 251
− 0
View file @ 8feb4fc7
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pcie_tlp is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
rx_wb_stb_i : in std_logic;
rx_wb_bar_i : in std_logic;
rx_wb_dat_i : in std_logic_vector(31 downto 0);
rx_wb_stall_o : out std_logic;
wb_stb_o : out std_logic;
wb_adr_o : out std_logic_vector(63 downto 0);
wb_we_o : out std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_o : out std_logic_vector(3 downto 0);
wb_stall_i : in std_logic);
end pcie_tlp;
architecture rtl of pcie_tlp is
type state_type is (h0, h_completion1, h_completion2, h_request, h_high_addr, h_low_addr, p_w0, p_wx, p_we, p_r0, p_rx, p_re);
signal state : state_type := h0;
signal progress : std_logic;
-- Bar0 Registers
-- signal csr : std_logic_vector(63 downto 0); -- bit0: CYC
-- signal error : std_logic_vector(63 downto 0);
-- signal address : std_logic_vector(63 downto 0);
-- signal sdwb : std_logic_vector(63 downto 0);
-- Header fields
signal s_fmttype : std_logic_vector(7 downto 0);
signal s_length : unsigned(9 downto 0);
signal s_transaction : std_logic_vector(23 downto 0);
signal s_last_be : std_logic_vector(3 downto 0);
signal s_first_be : std_logic_vector(3 downto 0);
signal r_fmttype : std_logic_vector(7 downto 0);
signal r_length : unsigned(9 downto 0);
signal r_transaction : std_logic_vector(23 downto 0);
signal r_last_be : std_logic_vector(3 downto 0);
signal r_first_be : std_logic_vector(3 downto 0);
signal r_address : std_logic_vector(63 downto 0);
-- Common subexpressions:
signal s_length_m1 : unsigned(9 downto 0);
signal s_length_eq1, s_length_eq2 : boolean;
signal s_address_p4 : std_logic_vector(63 downto 0);
-- Stall bypass mux
signal r_always_stall, r_never_stall : std_logic;
begin
wb_adr_o <= r_address;
wb_dat_o <= rx_wb_dat_i;
rx_wb_stall_o <= r_always_stall or (not r_never_stall and wb_stall_i);
-- Fields in the rx_data
s_fmttype <= rx_wb_dat_i(31 downto 24);
s_length <= unsigned(rx_wb_dat_i(9 downto 0));
s_transaction <= rx_wb_dat_i(31 downto 8);
s_last_be <= rx_wb_dat_i(7 downto 4);
s_first_be <= rx_wb_dat_i(3 downto 0);
s_length_m1 <= r_length - 1;
s_length_eq1 <= r_length = 1;
s_length_eq2 <= r_length = 2;
s_address_p4 <= r_address(63 downto 24) &
std_logic_vector(unsigned(r_address(23 downto 0)) + to_unsigned(4, 24));
state_machine : process(clk_i) is
variable next_state : state_type;
begin
if rising_edge(clk_i) then
if rstn_i = '0' then
state <= h0;
else
----------------- Pre-transition actions --------------------
case state is
when h0 =>
r_fmttype <= s_fmttype;
r_length <= s_length;
when h_completion1 => null;
when h_completion2 =>
r_transaction <= s_transaction;
when h_request =>
r_transaction <= s_transaction;
r_last_be <= s_last_be;
r_first_be <= s_first_be;
r_address <= (others => '0');
when h_high_addr =>
r_address(63 downto 32) <= rx_wb_dat_i(31 downto 0);
when h_low_addr =>
-- address also stores busnum/devnum/ext/reg for IO ops
r_address(31 downto 2) <= rx_wb_dat_i(31 downto 2);
when p_w0 => null;
when p_wx => null;
when p_we => null;
when p_r0 => null;
when p_rx => null;
when p_re => null;
end case;
----------------- Transition rules --------------------
next_state := state;
case state is
when h0 =>
if rx_wb_stb_i = '1' then
if s_fmttype(3) = '1' then
next_state := h_completion1;
else
next_state := h_request;
end if;
end if;
when h_completion1 =>
if rx_wb_stb_i = '1' then
next_state := h_completion2;
end if;
when h_completion2 =>
if rx_wb_stb_i = '1' then
if r_fmttype(6) = '1' then
next_state := p_w0; -- !!! go to some other state
else
next_state := h0;
end if;
end if;
when h_request =>
if rx_wb_stb_i = '1' then
if r_fmttype(5) = '1' then
next_state := h_high_addr;
else
next_state := h_low_addr;
end if;
end if;
when h_high_addr =>
if rx_wb_stb_i = '1' then
next_state := h_low_addr;
end if;
when h_low_addr =>
if rx_wb_stb_i = '1' then
if r_fmttype(6) = '1' then
next_state := p_w0;
else
next_state := p_r0;
end if;
end if;
when p_w0 =>
if (rx_wb_stb_i and not wb_stall_i) = '1' then
if s_length_eq1 then
next_state := h0;
elsif s_length_eq2 then
next_state := p_we;
else
next_state := p_wx;
end if;
r_length <= s_length_m1;
r_address <= s_address_p4;
end if;
when p_wx =>
if (rx_wb_stb_i and not wb_stall_i) = '1' then
if s_length_eq2 then
next_state := p_we;
end if;
r_length <= s_length_m1;
r_address <= s_address_p4;
end if;
when p_we =>
if (rx_wb_stb_i and not wb_stall_i) = '1' then
next_state := h0;
end if;
when p_r0 =>
if (not wb_stall_i) = '1' then
if s_length_eq1 then
next_state := h0;
elsif s_length_eq2 then
next_state := p_re;
else
next_state := p_rx;
end if;
r_length <= s_length_m1;
r_address <= s_address_p4;
end if;
when p_rx =>
if (not wb_stall_i) = '1' then
if s_length_eq2 then
next_state := p_re;
end if;
r_length <= s_length_m1;
r_address <= s_address_p4;
end if;
when p_re =>
if (not wb_stall_i) = '1' then
next_state := h0;
end if;
end case;
----------------- Post-transition actions --------------------
wb_stb_o <= '0';
wb_we_o <= 'X';
wb_sel_o <= (others => 'X');
r_always_stall <= '0';
r_never_stall <= '1' ;
state <= next_state;
case next_state is
when h0 => null;
when h_completion1 => null;
when h_completion2 => null;
when h_request => null;
when h_high_addr => null;
when h_low_addr => null;
when p_w0 =>
r_never_stall <= '0';
wb_stb_o <= rx_wb_stb_i;
wb_sel_o <= r_first_be;
wb_we_o <= '1';
when p_wx =>
r_never_stall <= '0';
wb_stb_o <= rx_wb_stb_i;
wb_sel_o <= x"f";
wb_we_o <= '1';
when p_we =>
r_never_stall <= '0';
wb_stb_o <= rx_wb_stb_i;
wb_sel_o <= r_last_be;
wb_we_o <= '1';
when p_r0 =>
r_always_stall <= '1';
wb_stb_o <= '1';
wb_sel_o <= r_first_be;
wb_we_o <= '0';
when p_rx =>
r_always_stall <= '1';
wb_stb_o <= '1';
wb_sel_o <= x"f";
wb_we_o <= '0';
when p_re =>
r_always_stall <= '1';
wb_stb_o <= '1';
wb_sel_o <= r_last_be;
wb_we_o <= '0';
end case;
end if;
end if;
end process;
end rtl;
hdl/pcie_wb.qsf
+ 333
− 619
View file @ 8feb4fc7
This diff is collapsed.
hdl/pcie_wb.vhd
+ 30
− 10
View file @ 8feb4fc7
......@@ -39,11 +39,13 @@ architecture rtl of pcie_wb is
signal count : unsigned(26 downto 0) := to_unsigned(0, 27);
signal led_r : std_logic := '0';
signal locked, pow_rstn, rstn, stall : std_logic;
signal locked, pow_rstn, phy_rstn, rstn, stall : std_logic;
constant stall_pattern : std_logic_vector(15 downto 0) := "1111010110111100";
signal stall_idx : unsigned(3 downto 0);
signal rx_wb_stb, rx_wb_stall : std_logic;
signal rx_wb_dat : std_logic_vector(31 downto 0);
begin
reset : pow_reset
......@@ -59,23 +61,41 @@ begin
c0 => cal_blk_clk,
locked => locked);
rstn <= pow_rstn and locked;
phy_rstn <= pow_rstn and locked;
pcie_phy : pcie_altera port map(
clk125_i => clk125_i,
cal_clk50_i => cal_blk_clk,
rstn_i => rstn,
rstn_o => open,
rstn_i => phy_rstn,
rstn_o => rstn,
pcie_refclk_i => pcie_refclk_i,
pcie_rstn_i => pcie_rstn_i,
pcie_rx_i => pcie_rx_i,
pcie_tx_o => pcie_tx_o,
-- rest open for now
wb_clk_o => wb_clk,
rx_wb_stall_i => stall,
tx_wb_stb_i => '0',
tx_wb_dat_i => (others => '0')
);
wb_clk_o => wb_clk,
rx_wb_stb_o => rx_wb_stb,
rx_wb_dat_o => rx_wb_dat,
rx_wb_stall_i => rx_wb_stall,
-- No TX... yet.
tx_wb_stb_i => '0',
tx_wb_dat_i => (others => '0'),
tx_wb_stall_o => open);
pcie_logic : pcie_tlp port map(
clk_i => wb_clk,
rstn_i => rstn,
rx_wb_stb_i => rx_wb_stb,
rx_wb_bar_i => '0',
rx_wb_dat_i => rx_wb_dat,
rx_wb_stall_o => rx_wb_stall,
wb_stb_o => open,
wb_adr_o => open,
wb_we_o => open,
wb_dat_o => open,
wb_sel_o => open,
wb_stall_i => stall);
blink : process(wb_clk)
begin
......
hdl/pcie_wb_pkg.vhd
+ 18
− 0
View file @ 8feb4fc7
......@@ -28,4 +28,22 @@ package pcie_wb_pkg is
tx_wb_dat_i : in std_logic_vector(31 downto 0);
tx_wb_stall_o : out std_logic);
end component;
component pcie_tlp is
port(
clk_i : in std_logic;
rstn_i : in std_logic;
rx_wb_stb_i : in std_logic;
rx_wb_bar_i : in std_logic;
rx_wb_dat_i : in std_logic_vector(31 downto 0);
rx_wb_stall_o : out std_logic;
wb_stb_o : out std_logic;
wb_adr_o : out std_logic_vector(63 downto 0);
wb_we_o : out std_logic;
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_o : out std_logic_vector(3 downto 0);
wb_stall_i : in std_logic);
end component;
end pcie_wb_pkg;
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment