This reduces the required resources since we only use one set of adders for all channels (instead of one per).

There is no issue with multiple timestamps arriving simultaneously, since the previous stages serialise the
delivery of timestamps and this stage is fully pipelined, so it can process one timestamp per cycle.

[hdl] do not filter out falling edges in direct readout. This can be done if necessary by setting the relevant ACAM registers

Previous fix did not correctly account for when the most significant bit of a.frac was '1', as it would incorrectly consider it as a negative number.

Also updated the header notes.

deleted scripts for ucf generation; now all the spec generic pinout comes with the spec submodule and are applied in the syn Manifest

updated submodules;
added missing sim files

The following changes were done:

1. Point all submodules to new OHWR

2. update ddr3-sp6-core to latest master because the previous commit
(8618c1e154c322be34cb069b62d8293527744dda) was not available in OHWR. Please test!

3. remove etherbone-core

4. update general-cores to latest master and use the updated gc_ds182x_readout module