hdl: fix wrong polarity of TDC rst in reg_ctrl

d4b31206 · Dimitris Lampridis · 01673524 · d4b31206
Commit d4b31206 authored Dec 14, 2022 by Dimitris Lampridis
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reg_ctrl.vhd hdl/rtl/reg_ctrl.vhd +1 -1

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--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -423,7 +423,7 @@ begin
  process (clk_tdc_i)
  begin
    if rising_edge (clk_tdc_i) then
-      if rst_tdc_i = '1' then
+      if rst_tdc_n_i = '1' then
        ctrl_reg_d <= (others =>'0');
      else
        ctrl_reg_d <= ctrl_reg;