Commit 01673524 authored by Dimitris Lampridis's avatar Dimitris Lampridis

migrate to common CI and add CI for fpga bitstreams

parent 9f03ccce
......@@ -11,7 +11,6 @@ modelsim.ini
*.vstf
work
*.bak
hdl/syn/*
transcript
work/
NullFile
......
......@@ -4,12 +4,15 @@
variables:
GIT_SUBMODULE_STRATEGY: normal
EDL_CI_DOC_SRC_PATH: 'doc'
EDL_CI_DOC_DST_PATH: '$EDL_CI_EOS_OUTPUT_DIR/doc'
include:
- project: 'be-cem-edl/evergreen/gitlab-ci'
ref: master
file:
- 'edl-gitlab-ci.yml'
- local: 'hdl/syn/.gitlab-ci.yml'
cppcheck:
stage: analyse
......@@ -25,18 +28,6 @@ flawfinder:
script:
- make -C software/tools flawfinder
documentation:
stage: build
image:
name: gitlab-registry.cern.ch/coht/common-containers/documentation:latest
script:
- make -C doc html
- mkdir -p $EDL_CI_EOS_OUTPUT_DIR
- cp -a doc/_build/html/* $EDL_CI_EOS_OUTPUT_DIR
artifacts:
paths:
- $EDL_CI_EOS_OUTPUT_DIR
.script_fetch_kernel_dep: &script_fetch_kernel_dep
- git clone -b v1.1.5 --depth 1 https://ohwr.org/project/fmc-sw.git ~/git/fmc
- export FMC=~/git/fmc
......
breathe
docutils
Sphinx
sphinx
sphinx-rtd-theme
sphinx-autodoc-typehints
# SPDX-FileCopyrightText: 2022 CERN (home.cern)
#
# SPDX-License-Identifier: LGPL-2.1-or-later
variables:
_FMC_TDC_BITSTREAM_DEST: $CI_PROJECT_DIR/$EDL_CI_EOS_OUTPUT_DIR/bitstreams
.syn_template: &syn_template
interruptible: true
stage: build
needs: []
tags:
- xilinx_ise
- "14.7"
script:
- git submodule init && git submodule update
- cd hdl/syn/"$SYN_NAME"/
- hdlmake
- make
- |
if [[ $(cat *.par | grep -c "All constraints were met") = 0 ]]
then
echo -e "\e[31mTiming errors detected in PAR report. Aborting...\e[0m"
exit 1
fi
- tar -cJf $SYN_NAME.tar.xz *.syr *.par *.twr *.bit *.bin
- mkdir -p $_FMC_TDC_BITSTREAM_DEST
- cp $SYN_NAME.tar.xz $_FMC_TDC_BITSTREAM_DEST
artifacts:
name: "$SYN_NAME-synthesis-$CI_JOB_NAME-$CI_COMMIT_REF_NAME"
paths:
- $_FMC_TDC_BITSTREAM_DEST/*
SPEC synthesis:
variables:
SYN_NAME: "spec"
<<: *syn_template
SVEC synthesis:
variables:
SYN_NAME: "svec"
<<: *syn_template
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