Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC TDC 1ns 5cha
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
1
Merge Requests
1
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC TDC 1ns 5cha
Commits
6fbfbd34
Commit
6fbfbd34
authored
Mar 26, 2015
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
rtl: compile fixes for system-clock synchronous redesign of the core
parent
5f48c026
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
9 changed files
with
190 additions
and
165 deletions
+190
-165
Manifest.py
hdl/rtl/Manifest.py
+9
-2
circular_buffer.vhd
hdl/rtl/circular_buffer.vhd
+1
-2
data_engine.vhd
hdl/rtl/data_engine.vhd
+3
-1
fmc_tdc_core.vhd
hdl/rtl/fmc_tdc_core.vhd
+7
-6
fmc_tdc_mezzanine.vhd
hdl/rtl/fmc_tdc_mezzanine.vhd
+3
-3
fmc_tdc_wrapper.vhd
hdl/rtl/fmc_tdc_wrapper.vhd
+113
-92
leds_manager.vhd
hdl/rtl/leds_manager.vhd
+3
-3
reg_ctrl.vhd
hdl/rtl/reg_ctrl.vhd
+2
-2
tdc_core_pkg.vhd
hdl/rtl/tdc_core_pkg.vhd
+49
-54
No files found.
hdl/rtl/Manifest.py
View file @
6fbfbd34
files
=
[
"acam_databus_interface.vhd"
,
files
=
[
"tdc_core_pkg.vhd"
,
"acam_databus_interface.vhd"
,
"acam_timecontrol_interface.vhd"
,
"carrier_info.vhd"
,
"circular_buffer.vhd"
,
...
...
@@ -16,5 +18,10 @@ files = ["acam_databus_interface.vhd",
"reg_ctrl.vhd"
,
"start_retrig_ctrl.vhd"
,
"tdc_eic.vhd"
,
"wrabbit_sync.vhd"
];
"wrabbit_sync.vhd"
,
"fmc_tdc_direct_readout.vhd"
,
"fmc_tdc_direct_readout_slave.vhd"
,
"fmc_tdc_direct_readout_slave_pkg.vhd"
,
"fmc_tdc_wrapper.vhd"
,
];
hdl/rtl/circular_buffer.vhd
View file @
6fbfbd34
...
...
@@ -274,7 +274,6 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
tdc_mem_wb_stall_o
<=
'0'
;
gen_mem_blocks
:
for
i
in
0
to
3
generate
memory_block
:
generic_dpram
...
...
@@ -296,7 +295,7 @@ begin
db_i
=>
tdc_mem_wb_dat_i
,
qb_o
=>
mb_data
(
i
));
tstamp_rd_we
(
i
)
<=
'1'
when
unsigned
(
tdc_mem_wb_adr_i
(
1
downto
0
)
=
i
)
else
'0'
;
tstamp_rd_we
(
i
)
<=
'1'
when
unsigned
(
tdc_mem_wb_adr_i
(
1
downto
0
)
)
=
i
else
'0'
;
process
(
clk_sys_i
)
begin
...
...
hdl/rtl/data_engine.vhd
View file @
6fbfbd34
...
...
@@ -83,6 +83,8 @@ use work.tdc_core_pkg.all; -- definitions of types, constants, entities
--=================================================================================================
entity
data_engine
is
generic
(
g_simulation
:
boolean
);
port
-- INPUTS
-- Signals from the clk_rst_manager
...
...
@@ -806,7 +808,7 @@ begin
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
time_c_rst
,
counter_top_i
=>
x"0EE6B280"
,
counter_top_i
=>
f_pick
(
g_simulation
,
x"00005000"
,
x"0EE6B280"
)
,
counter_incr_en_i
=>
time_c_en
,
counter_is_full_o
=>
time_c_full_p
,
counter_o
=>
time_c
);
...
...
hdl/rtl/fmc_tdc_core.vhd
View file @
6fbfbd34
...
...
@@ -158,7 +158,7 @@ entity fmc_tdc_core is
generic
(
g_span
:
integer
:
=
32
;
-- address span in bus interfaces
g_width
:
integer
:
=
32
;
-- data width in bus interfaces
values_for_simul
:
boolean
:
=
FALSE
);
-- this generic is set to TRUE
g_simulation
:
boolean
:
=
FALSE
);
-- this generic is set to TRUE
-- when instantiated in a test-bench
port
(
...
...
@@ -402,10 +402,8 @@ begin
starting_utc_i
=>
starting_utc
,
local_utc_o
=>
local_utc
,
local_utc_p_o
=>
local_utc_p
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_period
<=
c_SIM_CLK_PERIOD
when
values_for_simul
else
c_SYN_CLK_PERIOD
;
clk_period
<=
f_pick
(
g_simulation
,
c_SIM_CLK_PERIOD
,
c_SYN_CLK_PERIOD
);
---------------------------------------------------------------------------------------------------
-- ACAM TIMECONTROL INTERFACE --
---------------------------------------------------------------------------------------------------
...
...
@@ -479,6 +477,8 @@ begin
-- DATA ENGINE --
---------------------------------------------------------------------------------------------------
data_engine_block
:
data_engine
generic
map
(
g_simulation
=>
g_simulation
)
port
map
(
acam_ack_i
=>
acm_ack
,
acam_dat_i
=>
acm_dat_r
,
...
...
@@ -533,7 +533,7 @@ begin
acam_tstamp2_i
=>
acam_tstamp2
,
acam_tstamp2_ok_p_i
=>
acam_tstamp2_ok_p
,
dacapo_c_rst_p_i
=>
clear_dacapo_counter
,
deactivate_chan_i
=>
deactivate_chan
,
deactivate_chan_i
=>
deactivate_chan
,
roll_over_incr_recent_i
=>
roll_over_incr_recent
,
clk_i_cycles_offset_i
=>
clk_i_cycles_offset
,
roll_over_nb_i
=>
roll_over_nb
,
...
...
@@ -581,6 +581,7 @@ begin
port
map
(
clk_tdc_i
=>
clk_tdc_i
,
clk_sys_i
=>
clk_sys_i
,
rst_n_sys_i
=>
rst_n_sys_i
,
tstamp_wr_rst_i
=>
rst_tdc_i
,
tstamp_wr_adr_i
=>
circ_buff_class_adr
,
tstamp_wr_cyc_i
=>
circ_buff_class_cyc
,
...
...
@@ -606,7 +607,7 @@ begin
TDCboard_leds
:
leds_manager
generic
map
(
g_width
=>
32
,
values_for_simul
=>
values_for_simul
)
g_simulation
=>
g_simulation
)
port
map
(
clk_i
=>
clk_tdc_i
,
rst_i
=>
rst_tdc_i
,
...
...
hdl/rtl/fmc_tdc_mezzanine.vhd
View file @
6fbfbd34
...
...
@@ -109,7 +109,7 @@ entity fmc_tdc_mezzanine is
(
g_with_wrabbit_core
:
boolean
:
=
FALSE
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
g_simulation
:
boolean
:
=
FALSE
);
port
-- TDC core
(
...
...
@@ -314,7 +314,7 @@ begin
generic
map
(
g_span
=>
g_span
,
g_width
=>
g_width
,
values_for_simul
=>
FALSE
)
g_simulation
=>
g_simulation
)
port
map
(
-- clks, rst
clk_tdc_i
=>
clk_tdc_i
,
...
...
@@ -387,7 +387,7 @@ begin
---------------------------------------------------------------------------------------------------
cmp_wrabbit_synch
:
wrabbit_sync
generic
map
(
g_simulation
=>
false
,
(
g_simulation
=>
g_simulation
,
g_with_wrabbit_core
=>
g_with_wrabbit_core
)
port
map
(
clk_sys_i
=>
clk_sys_i
,
...
...
hdl/rtl/fmc_tdc_wrapper.vhd
View file @
6fbfbd34
This diff is collapsed.
Click to expand it.
hdl/rtl/leds_manager.vhd
View file @
6fbfbd34
...
...
@@ -93,7 +93,7 @@ use work.gencores_pkg.all;
entity
leds_manager
is
generic
(
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
g_simulation
:
boolean
:
=
FALSE
);
port
-- INPUTS
-- Signals from the clks_rsts_manager
...
...
@@ -167,7 +167,7 @@ begin
end
if
;
end
process
;
visible_blink_length
<=
c_BLINK_LGTH_SIM
when
values_for_simul
else
c_BLINK_LGTH_SYN
;
visible_blink_length
<=
c_BLINK_LGTH_SIM
when
g_simulation
else
c_BLINK_LGTH_SYN
;
---------------------------------------------------------------------------------------------------
...
...
@@ -315,4 +315,4 @@ begin
end
rtl
;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
\ No newline at end of file
----------------------------------------------------------------------------------------------------
hdl/rtl/reg_ctrl.vhd
View file @
6fbfbd34
...
...
@@ -341,8 +341,8 @@ begin
one_hz_phase
<=
(
others
=>
'0'
);
wrabbit_ctrl_reg
<=
(
others
=>
'0'
);
deactivate_chan
<=
(
others
=>
'0'
);
irq_tstamp_threshold
<=
x"00000
100
"
;
-- default 256 timestamps: full memory
irq_time_threshold
<=
x"000000
C8
"
;
-- default 200 ms
irq_tstamp_threshold
<=
x"00000
001
"
;
-- default 256 timestamps: full memory
irq_time_threshold
<=
x"000000
01
"
;
-- default 200 ms
dac_word
<=
c_DEFAULT_DAC_WORD
;
-- default DAC Vout = 1.65
elsif
wb_in
.
cyc
=
'1'
and
wb_in
.
stb
=
'1'
and
wb_in
.
we
=
'1'
then
...
...
hdl/rtl/tdc_core_pkg.vhd
View file @
6fbfbd34
...
...
@@ -156,7 +156,7 @@ package tdc_core_pkg is
constant
c_TDC_CONFIG_SDB_DEVICE
:
t_sdb_device
:
=
(
abi_class
=>
x"0000"
,
-- undocumented device
abi_ver_major
=>
x"0
1
"
,
abi_ver_major
=>
x"0
2
"
,
abi_ver_minor
=>
x"01"
,
wbd_endian
=>
c_sdb_endian_big
,
wbd_width
=>
x"4"
,
-- 32-bit port granularity
...
...
@@ -195,7 +195,7 @@ package tdc_core_pkg is
constant
c_SYN_CLK_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"07735940"
;
-- for simulation: 1 msec = x"0001E848" clk_i cycles (1 clk_i cycle = 8ns)
constant
c_SIM_CLK_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"000
1E848
"
;
constant
c_SIM_CLK_PERIOD
:
std_logic_vector
(
31
downto
0
)
:
=
x"000
01000
"
;
---------------------------------------------------------------------------------------------------
...
...
@@ -344,7 +344,7 @@ package tdc_core_pkg is
(
g_with_wrabbit_core
:
boolean
:
=
TRUE
;
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
g_simulation
:
boolean
:
=
FALSE
);
port
-- TDC core
(
...
...
@@ -437,7 +437,7 @@ package tdc_core_pkg is
generic
(
g_span
:
integer
:
=
32
;
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
g_simulation
:
boolean
:
=
FALSE
);
port
(
clk_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
...
...
@@ -605,6 +605,8 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component
data_engine
generic
(
g_simulation
:
boolean
);
port
(
acam_ack_i
:
in
std_logic
;
acam_dat_i
:
in
std_logic_vector
(
31
downto
0
);
...
...
@@ -725,7 +727,6 @@ package tdc_core_pkg is
component
data_formatting
port
(
tstamp_wr_wb_ack_i
:
in
std_logic
;
tstamp_wr_dat_i
:
in
std_logic_vector
(
127
downto
0
);
acam_tstamp1_i
:
in
std_logic_vector
(
31
downto
0
);
acam_tstamp1_ok_p_i
:
in
std_logic
;
acam_tstamp2_i
:
in
std_logic_vector
(
31
downto
0
);
...
...
@@ -862,7 +863,7 @@ package tdc_core_pkg is
component
leds_manager
is
generic
(
g_width
:
integer
:
=
32
;
values_for_simul
:
boolean
:
=
FALSE
);
g_simulation
:
boolean
:
=
FALSE
);
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
...
...
@@ -911,55 +912,36 @@ package tdc_core_pkg is
---------------------------------------------------------------------------------------------------
component
circular_buffer
port
(
clk_tdc_i
:
in
std_logic
;
-- 125 MHz clock; same for both port
clk_sys_i
:
in
std_logic
;
tstamp_wr_rst_i
:
in
std_logic
;
tstamp_wr_stb_i
:
in
std_logic
;
tstamp_wr_cyc_i
:
in
std_logic
;
tstamp_wr_we_i
:
in
std_logic
;
tstamp_wr_adr_i
:
in
std_logic_vector
(
7
downto
0
);
tstamp_wr_dat_i
:
in
std_logic_vector
(
127
downto
0
);
tdc_mem_wb_rst_i
:
in
std_logic
;
tdc_mem_wb_stb_i
:
in
std_logic
;
tdc_mem_wb_cyc_i
:
in
std_logic
;
tdc_mem_wb_we_i
:
in
std_logic
;
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
--------------------------------------------------
tstamp_wr_ack_p_o
:
out
std_logic
;
tstamp_wr_dat_o
:
out
std_logic_vector
(
127
downto
0
);
tdc_mem_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stall_o
:
out
std_logic
);
--------------------------------------------------
end
component
;
---------------------------------------------------------------------------------------------------
component
blk_mem_circ_buff_v6_4
port
(
clka
:
in
std_logic
;
addra
:
in
std_logic_vector
(
7
downto
0
);
dina
:
in
std_logic_vector
(
127
downto
0
);
ena
:
in
std_logic
;
wea
:
in
std_logic_vector
(
0
downto
0
);
clkb
:
in
std_logic
;
addrb
:
in
std_logic_vector
(
9
downto
0
);
dinb
:
in
std_logic_vector
(
31
downto
0
);
enb
:
in
std_logic
;
web
:
in
std_logic_vector
(
0
downto
0
);
--------------------------------------------------
douta
:
out
std_logic_vector
(
127
downto
0
);
doutb
:
out
std_logic_vector
(
31
downto
0
));
--------------------------------------------------
component
circular_buffer
port
(
clk_tdc_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
rst_n_sys_i
:
in
std_logic
;
tstamp_wr_rst_i
:
in
std_logic
;
tstamp_wr_stb_i
:
in
std_logic
;
tstamp_wr_cyc_i
:
in
std_logic
;
tstamp_wr_we_i
:
in
std_logic
;
tstamp_wr_adr_i
:
in
std_logic_vector
(
7
downto
0
);
tstamp_wr_dat_i
:
in
std_logic_vector
(
127
downto
0
);
tdc_mem_wb_rst_i
:
in
std_logic
;
tdc_mem_wb_stb_i
:
in
std_logic
;
tdc_mem_wb_cyc_i
:
in
std_logic
;
tdc_mem_wb_we_i
:
in
std_logic
;
tdc_mem_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
tstamp_wr_ack_p_o
:
out
std_logic
;
tstamp_wr_dat_o
:
out
std_logic_vector
(
127
downto
0
);
tdc_mem_wb_ack_o
:
out
std_logic
;
tdc_mem_wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
tdc_mem_wb_stall_o
:
out
std_logic
);
end
component
;
component
fmc_tdc_wrapper
is
generic
(
g_simulation
:
boolean
);
g_simulation
:
boolean
:
=
false
;
g_with_direct_readout
:
boolean
:
=
false
);
port
(
clk_sys_i
:
in
std_logic
;
rst_sys_n_i
:
in
std_logic
;
...
...
@@ -1004,8 +986,10 @@ package tdc_core_pkg is
tdc_in_fpga_3_i
:
in
std_logic
;
tdc_in_fpga_4_i
:
in
std_logic
;
tdc_in_fpga_5_i
:
in
std_logic
;
mezz_scl_b
:
inout
std_logic
;
mezz_sda_b
:
inout
std_logic
;
mezz_scl_o
:
out
std_logic
;
mezz_sda_o
:
out
std_logic
;
mezz_scl_i
:
in
std_logic
;
mezz_sda_i
:
in
std_logic
;
mezz_one_wire_b
:
inout
std_logic
;
tm_link_up_i
:
in
std_logic
;
tm_time_valid_i
:
in
std_logic
;
...
...
@@ -1016,21 +1000,32 @@ package tdc_core_pkg is
tm_clk_dmtd_locked_i
:
in
std_logic
;
tm_dac_value_i
:
in
std_logic_vector
(
23
downto
0
);
tm_dac_wr_i
:
in
std_logic
;
slave_i
:
in
t_wishbone_slave_in
;
slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_master_out
;
slave_o
:
out
t_wishbone_slave_out
;
direct_slave_i
:
in
t_wishbone_slave_in
;
direct_slave_i
:
in
t_wishbone_slave_in
:
=
cc_dummy_master_out
;
direct_slave_o
:
out
t_wishbone_slave_out
;
irq_o
:
out
std_logic
;
clk_125m_tdc_o
:
out
std_logic
);
end
component
fmc_tdc_wrapper
;
function
f_pick
(
cond
:
boolean
;
if_true
:
std_logic_vector
;
if_false
:
std_logic_vector
)
return
std_logic_vector
;
end
tdc_core_pkg
;
--=================================================================================================
-- package body
--=================================================================================================
package
body
tdc_core_pkg
is
function
f_pick
(
cond
:
boolean
;
if_true
:
std_logic_vector
;
if_false
:
std_logic_vector
)
return
std_logic_vector
is
begin
if
(
cond
)
then
return
if_true
;
else
return
if_false
;
end
if
;
end
f_pick
;
end
tdc_core_pkg
;
--=================================================================================================
-- package end
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment