rtl: moved full mezzanine wrapper code & direct readout module to the core sources directory

5f48c026 · Tomasz Wlostowski · 2d00d3ef · 5f48c026 · 5f48c026 · 5f48c026
Commit 5f48c026 authored Mar 26, 2015 by Tomasz Wlostowski
31 changed files
--- a/hdl/top/spec/fmc_tdc_direct_readout.vhd
+++ b/hdl/top/spec/fmc_tdc_direct_readout.vhd
--- a/hdl/top/spec/fmc_tdc_direct_readout_slave.vhd
+++ b/hdl/top/spec/fmc_tdc_direct_readout_slave.vhd
--- a/hdl/top/spec/fmc_tdc_direct_readout_slave_pkg.vhd
+++ b/hdl/top/spec/fmc_tdc_direct_readout_slave_pkg.vhd
--- a/hdl/top/spec/fmc_tdc_wrapper.vhd
+++ b/hdl/top/spec/fmc_tdc_wrapper.vhd
--- a/hdl/top/spec/tdc_core_pkg.vhd
+++ b/hdl/top/spec/tdc_core_pkg.vhd
--- a/hdl/top/spec/fmc_tdc_direct_readout_slave.wb
+++ b/hdl/top/spec/fmc_tdc_direct_readout_slave.wb
--- a/hdl/sim/spec/data_vectors/acam_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/acam_test_cmd0.vec
--- a/hdl/sim/spec/data_vectors/atdc_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/atdc_test_cmd0.vec
--- a/hdl/sim/spec/data_vectors/memo_test_cmd0.vec
+++ b/hdl/sim/spec/data_vectors/memo_test_cmd0.vec
--- a/hdl/sim/spec/data_vectors/pulses.txt
+++ b/hdl/sim/spec/data_vectors/pulses.txt
--- a/hdl/sim/spec/spec_fmc_tdc_sim.xise
+++ b/hdl/sim/spec/spec_fmc_tdc_sim.xise
--- a/hdl/sim/spec/testbench/acam_data_model.vhd
+++ b/hdl/sim/spec/testbench/acam_data_model.vhd
--- a/hdl/sim/spec/testbench/acam_fifo_model.vhd
+++ b/hdl/sim/spec/testbench/acam_fifo_model.vhd
--- a/hdl/sim/spec/testbench/acam_model.vhd
+++ b/hdl/sim/spec/testbench/acam_model.vhd
--- a/hdl/sim/spec/testbench/acam_timing_model.vhd
+++ b/hdl/sim/spec/testbench/acam_timing_model.vhd
--- a/hdl/sim/spec/testbench/gnum_model/cmd_router.vhd
+++ b/hdl/sim/spec/testbench/gnum_model/cmd_router.vhd
--- a/hdl/sim/spec/testbench/gnum_model/cmd_router1.vhd
+++ b/hdl/sim/spec/testbench/gnum_model/cmd_router1.vhd
--- a/hdl/sim/spec/testbench/gnum_model/gennum_tb.tar
+++ b/hdl/sim/spec/testbench/gnum_model/gennum_tb.tar
--- a/hdl/sim/spec/testbench/gnum_model/gn412x_bfm.vhd
+++ b/hdl/sim/spec/testbench/gnum_model/gn412x_bfm.vhd
--- a/hdl/sim/spec/testbench/gnum_model/mem_model.vhd
+++ b/hdl/sim/spec/testbench/gnum_model/mem_model.vhd
--- a/hdl/sim/spec/testbench/gnum_model/textutil.vhd
+++ b/hdl/sim/spec/testbench/gnum_model/textutil.vhd
--- a/hdl/sim/spec/testbench/gnum_model/util.vhd
+++ b/hdl/sim/spec/testbench/gnum_model/util.vhd
--- a/hdl/sim/spec/testbench/start_stop_gen.vhd
+++ b/hdl/sim/spec/testbench/start_stop_gen.vhd
--- a/hdl/sim/spec/testbench/tb_tdc.vhd
+++ b/hdl/sim/spec/testbench/tb_tdc.vhd
--- a/hdl/sim/svec/testbench/Manifest.py
+++ b/hdl/sim/svec/testbench/Manifest.py
--- a/hdl/sim/svec/testbench/main.sv
+++ b/hdl/sim/svec/testbench/main.sv
--- a/hdl/sim/svec/testbench/run.do
+++ b/hdl/sim/svec/testbench/run.do
--- a/hdl/sim/svec/testbench/wave.do
+++ b/hdl/sim/svec/testbench/wave.do
--- a/hdl/sim/svec/vme64x_bfm/components/sn74vmeh22501.v
+++ b/hdl/sim/svec/vme64x_bfm/components/sn74vmeh22501.v
--- a/hdl/sim/svec/vme64x_bfm/svec_vme_buffers.svh
+++ b/hdl/sim/svec/vme64x_bfm/svec_vme_buffers.svh
--- a/hdl/sim/svec/vme64x_bfm/vme64x_bfm.svh
+++ b/hdl/sim/svec/vme64x_bfm/vme64x_bfm.svh