FMC Time to Digital Converter Gateware
The Time to Digital Converter mezzanine board FMC TDC 1ns 5cha has 5
input channels. Its purpose is to calculate time differences between
pulses arriving to the channels with a precision of ±700 ps.
It follows the FMC architecture and can be carried by any carrier board
like the SPEC or the
SVEC. It is using a dedicated
time-to-digital converter chip
TDC-GPX
of the European company ACAM.
The carrier board, SPEC or SVEC, provides FPGA logic, power supplies,
clocking resources as well as the interface to the PCIe (SPEC) or VME64x
(SVEC) bus.
The TDC mezzanine board houses mainly the five input channels and the
ACAM time-to-digital converter chip.
Figure 1 shows the gateware architecture for the simpler case of the
SPEC carrier. Figure 2 zooms into the main module of Figure 1 depicted
in green.
As both figures show the design is highly modular and the
communication of all the modules with the PCIe interface is based on
WISHBONE.
https://www.ohwr.org/3012
Figure 1: SPEC TDC gateware architecture
The main parts of the design, as shown in Figure 1 are:
- The GN4124 core is the interface to the Gennum GN4124 PCIe bridge chip. The core provides a WISHBONE master where all the other FPGA modules can connect to and gain access to the PCIe.
- The 1-wire core communicates with the DS18B20 thermometer and unique ID chip on the SPEC.
- The carrier info core contains control and status registers related to the SPEC (e.g. PCB version).
- The FMC TDC mezzanine is the application specific part of the
design and includes all the modules essential for the communication
with the different parts of the TDC mezzanine board:
- the ACAM chip for the retrieval of the timestamps
- the input termination resistors
- the front panel LEDs
- the DS18B20 thermometer and unique ID chip
- the 24AA64 EEPROM memory chip
- the PLL AD9516 and DAC AD5662.
- The vector interrupt controller, VIC, is multiplexing different interrupt lines into one single line to the host.
- The crossbar is used to map the different slaves in the WISHBONE address space.
Figure 2 shows the different parts of the FMC TDC mezzanine module
and their connections to the TDC mezzanine board. The heart of this
module is the TDC core, depicted in pink.
The TDC core is first responsible for configuring the ACAM chip. The
configuration instructions are provided through the PCIe interface.
Once the ACAM chip is configured, rising edges arriving to any of its
channels are time-stamped. The TDC core is responsible for
retrieving the timestamps;
it is then putting them in a user-convenient format and finally it is
making them available to the PCIe
interface.
https://www.ohwr.org/3013
Figure 2: FMC TDC mezzanine gateware architecture