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  • Spec tdc release 7 0

Spec tdc release 7 0

Last edited by Grzegorz Daniluk Dec 19, 2017
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SPEC TDC Release 7.0



Binary

For TDC v3.1 on SPEC carrier


Memory map

See the "SPEC Memory Map" section of the Gateware Architecture Manual


Sources

Gateware

Gateware architecture


Release date

19.12.2017


Release notes

Important changes:

  • Redesigned clock tree. Now the Wishbone port of the TDC core is operating in the common system clock domain (no cross-clock transfer needed).
  • Redesigned readout: separate per-channel FIFO instead of a circular buffer.
  • Added last received pulse timestamp registers.
  • Added hardware timestamp sequencing.
  • Added per-channel input enable.
  • Updated the WR Core to the latest v4.2.
  • Updated gn4124-core to fix PCIe freezes
  • Dropped the non-WR version of the firmware.


_Back to the gateware release page_

T.Wlostowski, Greg Daniluk 19 December 2017

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