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FMC TDC 1ns 5cha - Gateware
Commit 7b2bad61 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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include WRPC LM32 firmware v2.1 for SVEC

parent 8597e333
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Showing with 4 additions and 4 deletions
hdl/syn/spec/wr_spec_tdc.xise
View file @ 7b2bad61
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
<!-- along with the project source files, is sufficient to open and --> <!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. --> <!-- implement in ISE Project Navigator. -->
<!-- --> <!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header> </header>
<autoManagedFiles> <autoManagedFiles>
...@@ -1137,6 +1137,6 @@ ...@@ -1137,6 +1137,6 @@
<bindings/> <bindings/>
<version xil_pn:ise_version="14.5" xil_pn:schema_version="2"/> <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project> </project>
hdl/syn/svec/wr_svec_tdc.xise
View file @ 7b2bad61
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
......
hdl/top/svec/wr_svec_tdc.vhd
View file @ 7b2bad61
...@@ -673,7 +673,7 @@ begin ...@@ -673,7 +673,7 @@ begin
g_with_external_clock_input => false, g_with_external_clock_input => false,
g_aux_clks => 2, g_aux_clks => 2,
g_ep_rxbuf_size => 1024, g_ep_rxbuf_size => 1024,
g_dpram_initf => "none", g_dpram_initf => "wrc.ram",
g_dpram_size => 90112/4, g_dpram_size => 90112/4,
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
......
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