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FMC TDC 1ns 5cha - Gateware
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FMC TDC 1ns 5cha - Gateware
Commits
7b2bad61
Commit
7b2bad61
authored
Jan 17, 2017
by
Evangelia Gousiou
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Plain Diff
include WRPC LM32 firmware v2.1 for SVEC
parent
8597e333
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3 changed files
with
4 additions
and
4 deletions
+4
-4
wr_spec_tdc.xise
hdl/syn/spec/wr_spec_tdc.xise
+2
-2
wr_svec_tdc.xise
hdl/syn/svec/wr_svec_tdc.xise
+1
-1
wr_svec_tdc.vhd
hdl/top/svec/wr_svec_tdc.vhd
+1
-1
No files found.
hdl/syn/spec/wr_spec_tdc.xise
View file @
7b2bad61
...
...
@@ -9,7 +9,7 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-201
2
Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-201
3
Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
...
...
@@ -1137,6 +1137,6 @@
<bindings/>
<version
xil_pn:ise_version=
"14.
5
"
xil_pn:schema_version=
"2"
/>
<version
xil_pn:ise_version=
"14.
7
"
xil_pn:schema_version=
"2"
/>
</project>
hdl/syn/svec/wr_svec_tdc.xise
View file @
7b2bad61
...
...
@@ -49,7 +49,7 @@
<property
xil_pn:name=
"Change Device Speed To"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Change Device Speed To Post Trace"
xil_pn:value=
"-3"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Combinatorial Logic Optimization"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Compile EDK Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile SIMPRIM (Timing) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile UNISIM (Functional) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Compile XilinxCoreLib (CORE Generator) Simulation Library"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
...
...
hdl/top/svec/wr_svec_tdc.vhd
View file @
7b2bad61
...
...
@@ -673,7 +673,7 @@ begin
g_with_external_clock_input
=>
false
,
g_aux_clks
=>
2
,
g_ep_rxbuf_size
=>
1024
,
g_dpram_initf
=>
"
none
"
,
g_dpram_initf
=>
"
wrc.ram
"
,
g_dpram_size
=>
90112
/
4
,
g_interface_mode
=>
PIPELINED
,
g_address_granularity
=>
BYTE
,
...
...
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