Reduced PFC
1 | Negative Power suplies Mounted/Not mounted | Not Mounted |
---|---|---|
2 | P5V switching regulator generating 5V or 3V7 | 3V7 |
3 | FPGA configured through SPI Flash or through the GN4124 SPRI interface | SPI Flash |
4 | GN4124 local bus clocked by PCIe clock or local oscillator | Local oscillator |
5 | GN4124 as PCIe 4x or PCIe 1x | 4x |
6 | GN4124 booting from serial eeprom or not | Boot from serial eeprom |
7 | Oscillators can be chosen between Rakon VT3205CR or Mercury VM53S3 | VT3205CR |
8 | VADJ fixed to 2V5 or variable | @ Fixed 2V5@ |
9 | VADJ enabled from power up or switched on by FPGA | Enabled from power up |
10 | Two parallel VTT Drivers for QDR and GN4124 or only one | One VTT driver |
11 | Power supplies switching frequency spread spectrum modulated or fixed | Spread spectrum |
12 | FPGA HSWAP tied to VADJ, P3V3, to GND or SPRI_XI_SWAP | To VADJ |
13 | SCANSTA112 bypassed | Not bypassed |
14 | SCANSTA112 full transparent mode disabled or enabled | Transparent mode enabled |
15 | FMC I2C Bus can be controlled either by FPGA, GN4124 I2C bus or GN4124 GPIOs | GN4124 GPIOs |
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