FPGA HSWAP tied to VADJ P3V3 to GND or SPRI XI SWAP
The status of the application FPGA IOs after power-up and during configuration is defined by the pin HWSWAP.
HSWAP high sets all IOs to high impedance. HSWAP low configures the IOs with a pull up to VCCO. As HWSWAP belongs to Bank 0, which is powered with VADJ, it is hard to predict what will be the FPGA IOs behaviour if VADJ is enabled after the FPGA is configured, in case the FPGA configuration is possible with VCCO_0 close to 0V.
For this reason we have forseen the following options:
* HSWAP high (high impedance on IOs)
- HSWAP connected to VADJ (R312 mounted)
- HSWAP connected to 3V3 (R328 mounted)
- HSWAP low (pull ups on IOs)
HSWAP to ground. R311 mounted.
- HSWAP controlled by GN4124 SPRI (R327 mounted)
Notice that if enabling VADJ after the application FPGA has been configured becomes problematic, there are also a couple of resistors that can enable VADJ from power up.
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