Case studies
A non exhaustive list of case studies is:
- 32 Bit TTL IO
- High Precision Time to Digital Converter (HPTDC) FMC
- Fine delay generator FMC
- DAC 100Ms/s 16Bits two channels. Function table of 1MS per channel
- ADC 200KS/s 16Bits 16 channels. Up to 16MS per channel
- ADC 1GS/s 8Bits 2 channels. 125KS/channel
Some of these case studies may not be feasible with the first carrier design. An analysis of each case follows:
32 Bit TTL IO
This design fits well into the specs of the standard FMC Vita 57 connector
High Precision Time to Digital Converter (HPTDC) FMC
CERN's HPTDC presents a readout interface of ~40 LVTTL pins clocked at 40MHz. This chip could fit without major problems in a Vita 57 FMC.
Fine delay generator FMC
Fine delay generators are normally based on an startable delay line oscillator locked to an stable clock reference and a programmable digital fine delay line. The startable oscillator normally contains a passive delay line of about 5ns which hardly fits into a Vita 57 FMC. Lateral connectors could allow mounting a 5ns coaxial cable.
DAC 100Ms/s 16Bits two channels. Function table of 1MS per channel
The application FPGA to Mezzanine interface will be 32 LVDS lines, plus some control lines. The DAC clock can be multiplexed either with CLK_C2M or an external clock.
ADC 200KS/s 16Bits 16 channels. Up to 16MS per channel
The total bit rate is only of 200KS/s*16Bit/S*16 Channels = 51.2MBit/s. The 16bit 16MS could be stored in the DDR3 module.
ADC 1GS/s 8Bits 2 channels. 125KS/channel
The desired data rate could be obtained with 32 LVDS pairs clocked at 500MHz.