Checking in files before merging branch

circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.csv

+BUSY0* BUSY_N_I<0> H23 "FMC_LA19_N" "P7";
+BUSY1* BUSY_N_I<1> C19 "FMC_LA14_N" "A2";
+BUSY2* BUSY_N_I<2> G16 "FMC_LA12_N" "C6";
+BUSY0 BUSY_P_I<0> H22 "FMC_LA19_P" "N6";
+BUSY1 BUSY_P_I<1> C18 "FMC_LA14_P" "B2";
+BUSY2 BUSY_P_I<2> G15 "FMC_LA12_P" "D6";
+BEAM_TRIGGER_CFD*<0> CFD_DISCR_N_I<0> H38 "FMC_LA32_N" "V15";
+BEAM_TRIGGER_CFD*<1> CFD_DISCR_N_I<1> H35 "FMC_LA30_N" "V12";
+BEAM_TRIGGER_CFD*<2> CFD_DISCR_N_I<2> H32 "FMC_LA28_N" "V11";
+BEAM_TRIGGER_CFD*<3> CFD_DISCR_N_I<3> H29 "FMC_LA24_N" "V8";
+BEAM_TRIGGER_CFD<0> CFD_DISCR_P_I<0> H37 "FMC_LA32_P" "U15";
+BEAM_TRIGGER_CFD<1> CFD_DISCR_P_I<1> H34 "FMC_LA30_P" "T12";
+BEAM_TRIGGER_CFD<2> CFD_DISCR_P_I<2> H31 "FMC_LA28_P" "U11";
+BEAM_TRIGGER_CFD<3> CFD_DISCR_P_I<3> H28 "FMC_LA24_P" "U8";
+CLK1* CLK_N_I<1> C27 "FMC_LA27_N" "T11";
+CLK2* CLK_N_I<2> H8 "FMC_LA02_N" "A15";
+CLK1 CLK_P_I<1> C26 "FMC_LA27_P" "R11";
+CLK2 CLK_P_I<2> H7 "FMC_LA02_P" "C15";
+CONT0* CONT_N_I<0> G25 "FMC_LA22_N" "T7";
+CONT1* CONT_N_I<1> C23 "FMC_LA18_CC_N" "T10";
+CONT2* CONT_N_I<2> H14 "FMC_LA07_N" "E8";
+CONT0 CONT_P_I<0> G24 "FMC_LA22_P" "R7";
+CONT1 CONT_P_I<1> C22 "FMC_LA18_CC_P" "R10";
+CONT2 CONT_P_I<2> H13 "FMC_LA07_P" "E7";
+DUT_CLK0* DUT_CLK_N_I<0> H26 "FMC_LA21_N" "V4";
+DUT_CLK0 DUT_CLK_P_I<0> H25 "FMC_LA21_P" "T4";
+SPARE1* SPARE_N_I<1> G13 "FMC_LA08_N" "E11";
+SPARE2* SPARE_N_I<2> H17 "FMC_LA11_N" "A12";
+SPARE1 SPARE_P_I<1> G12 "FMC_LA08_P" "F11";
+SPARE2 SPARE_P_I<2> H16 "FMC_LA11_P" "B12";
+BEAM_TRIGGER*<0> THRESHOLD_DISCR_N_I<0> G37 "FMC_LA33_N" "N9";
+BEAM_TRIGGER*<1> THRESHOLD_DISCR_N_I<1> G34 "FMC_LA31_N" "V6";
+BEAM_TRIGGER*<2> THRESHOLD_DISCR_N_I<2> G31 "FMC_LA29_N" "N8";
+BEAM_TRIGGER*<3> THRESHOLD_DISCR_N_I<3> G28 "FMC_LA25_N" "N11";
+BEAM_TRIGGER<0> THRESHOLD_DISCR_P_I<0> G36 "FMC_LA33_P" "M10";
+BEAM_TRIGGER<1> THRESHOLD_DISCR_P_I<1> G33 "FMC_LA31_P" "T6";
+BEAM_TRIGGER<2> THRESHOLD_DISCR_P_I<2> G30 "FMC_LA29_P" "M8";
+BEAM_TRIGGER<3> THRESHOLD_DISCR_P_I<3> G27 "FMC_LA25_P" "M11";
+TRIG0* TRIG_N_I<0> G22 "FMC_LA20_N" "P8";
+TRIG1* TRIG_N_I<1> G10 "FMC_LA03_N" "A13";
+TRIG2* TRIG_N_I<2> G19 "FMC_LA16_N" "A7";
+TRIG0 TRIG_P_I<0> G21 "FMC_LA20_P" "N7";
+TRIG1 TRIG_P_I<1> G9 "FMC_LA03_P" "C13";
+TRIG2 TRIG_P_I<2> G18 "FMC_LA16_P" "C7";
+HDMI_POWER_ENABLE1 HDMI_POWER_ENABLE1 H10 "FMC_LA04_P" "B16";
+HDMI_POWER_ENABLE2 HDMI_POWER_ENABLE2 H20 "FMC_LA15_N" "F9";
+FMC_LA*<2> FMC_LA*<2> G3 "FMC_CLK1_M2C_N" "V9";
+FMC_LA<2> FMC_LA<2> G2 "FMC_CLK1_M2C_P" "T9";
+FMC_LA<29> FMC_LA<29> G6 "FMC_LA00_CC_P" "D9";
+FRONT_PANEL_CLK FRONT_PANEL_CLK H4 "FMC_CLK0_M2C_P" "C10";
+FRONT_PANEL_CLK* FRONT_PANEL_CLK* H5 "FMC_CLK0_M2C_N" “A10”;

circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.ucf

+NET "BUSY_N_I<0>"  LOC = "P7"; ##  "FMC_LA19_N"  ,  H23  on FMC
+NET "BUSY_N_I<1>"  LOC = "A2"; ##  "FMC_LA14_N"  ,  C19  on FMC
+NET "BUSY_N_I<2>"  LOC = "C6"; ##  "FMC_LA12_N"  ,  G16  on FMC
+NET "BUSY_P_I<0>"  LOC = "N6"; ##  "FMC_LA19_P"  ,  H22  on FMC
+NET "BUSY_P_I<1>"  LOC = "B2"; ##  "FMC_LA14_P"  ,  C18  on FMC
+NET "BUSY_P_I<2>"  LOC = "D6"; ##  "FMC_LA12_P"  ,  G15  on FMC
+NET "CFD_DISCR_N_I<0>"  LOC = "V15"; ##  "FMC_LA32_N"  ,  H38  on FMC
+NET "CFD_DISCR_N_I<1>"  LOC = "V12"; ##  "FMC_LA30_N"  ,  H35  on FMC
+NET "CFD_DISCR_N_I<2>"  LOC = "V11"; ##  "FMC_LA28_N"  ,  H32  on FMC
+NET "CFD_DISCR_N_I<3>"  LOC = "V8"; ##  "FMC_LA24_N"  ,  H29  on FMC
+NET "CFD_DISCR_P_I<0>"  LOC = "U15"; ##  "FMC_LA32_P"  ,  H37  on FMC
+NET "CFD_DISCR_P_I<1>"  LOC = "T12"; ##  "FMC_LA30_P"  ,  H34  on FMC
+NET "CFD_DISCR_P_I<2>"  LOC = "U11"; ##  "FMC_LA28_P"  ,  H31  on FMC
+NET "CFD_DISCR_P_I<3>"  LOC = "U8"; ##  "FMC_LA24_P"  ,  H28  on FMC
+NET "CLK_N_I<1>"  LOC = "T11"; ##  "FMC_LA27_N"  ,  C27  on FMC
+NET "CLK_N_I<2>"  LOC = "A15"; ##  "FMC_LA02_N"  ,  H8  on FMC
+NET "CLK_P_I<1>"  LOC = "R11"; ##  "FMC_LA27_P"  ,  C26  on FMC
+NET "CLK_P_I<2>"  LOC = "C15"; ##  "FMC_LA02_P"  ,  H7  on FMC
+NET "CONT_N_I<0>"  LOC = "T7"; ##  "FMC_LA22_N"  ,  G25  on FMC
+NET "CONT_N_I<1>"  LOC = "T10"; ##  "FMC_LA18_CC_N"  ,  C23  on FMC
+NET "CONT_N_I<2>"  LOC = "E8"; ##  "FMC_LA07_N"  ,  H14  on FMC
+NET "CONT_P_I<0>"  LOC = "R7"; ##  "FMC_LA22_P"  ,  G24  on FMC
+NET "CONT_P_I<1>"  LOC = "R10"; ##  "FMC_LA18_CC_P"  ,  C22  on FMC
+NET "CONT_P_I<2>"  LOC = "E7"; ##  "FMC_LA07_P"  ,  H13  on FMC
+NET "DUT_CLK_N_I<0>"  LOC = "V4"; ##  "FMC_LA21_N"  ,  H26  on FMC
+NET "DUT_CLK_P_I<0>"  LOC = "T4"; ##  "FMC_LA21_P"  ,  H25  on FMC
+NET "SPARE_N_I<1>"  LOC = "E11"; ##  "FMC_LA08_N"  ,  G13  on FMC
+NET "SPARE_N_I<2>"  LOC = "A12"; ##  "FMC_LA11_N"  ,  H17  on FMC
+NET "SPARE_P_I<1>"  LOC = "F11"; ##  "FMC_LA08_P"  ,  G12  on FMC
+NET "SPARE_P_I<2>"  LOC = "B12"; ##  "FMC_LA11_P"  ,  H16  on FMC
+NET "THRESHOLD_DISCR_N_I<0>"  LOC = "N9"; ##  "FMC_LA33_N"  ,  G37  on FMC
+NET "THRESHOLD_DISCR_N_I<1>"  LOC = "V6"; ##  "FMC_LA31_N"  ,  G34  on FMC
+NET "THRESHOLD_DISCR_N_I<2>"  LOC = "N8"; ##  "FMC_LA29_N"  ,  G31  on FMC
+NET "THRESHOLD_DISCR_N_I<3>"  LOC = "N11"; ##  "FMC_LA25_N"  ,  G28  on FMC
+NET "THRESHOLD_DISCR_P_I<0>"  LOC = "M10"; ##  "FMC_LA33_P"  ,  G36  on FMC
+NET "THRESHOLD_DISCR_P_I<1>"  LOC = "T6"; ##  "FMC_LA31_P"  ,  G33  on FMC
+NET "THRESHOLD_DISCR_P_I<2>"  LOC = "M8"; ##  "FMC_LA29_P"  ,  G30  on FMC
+NET "THRESHOLD_DISCR_P_I<3>"  LOC = "M11"; ##  "FMC_LA25_P"  ,  G27  on FMC
+NET "TRIG_N_I<0>"  LOC = "P8"; ##  "FMC_LA20_N"  ,  G22  on FMC
+NET "TRIG_N_I<1>"  LOC = "A13"; ##  "FMC_LA03_N"  ,  G10  on FMC
+NET "TRIG_N_I<2>"  LOC = "A7"; ##  "FMC_LA16_N"  ,  G19  on FMC
+NET "TRIG_P_I<0>"  LOC = "N7"; ##  "FMC_LA20_P"  ,  G21  on FMC
+NET "TRIG_P_I<1>"  LOC = "C13"; ##  "FMC_LA03_P"  ,  G9  on FMC
+NET "TRIG_P_I<2>"  LOC = "C7"; ##  "FMC_LA16_P"  ,  G18  on FMC
+NET "HDMI_POWER_ENABLE1"  LOC = "B16"; ##  "FMC_LA04_P"  ,  H10  on FMC
+NET "HDMI_POWER_ENABLE2"  LOC = "F9"; ##  "FMC_LA15_N"  ,  H20  on FMC
+NET "FMC_LA*<2>"  LOC = "V9"; ##  "FMC_CLK1_M2C_N"  ,  G3  on FMC
+NET "FMC_LA<2>"  LOC = "T9"; ##  "FMC_CLK1_M2C_P"  ,  G2  on FMC
+NET "FMC_LA<29>"  LOC = "D9"; ##  "FMC_LA00_CC_P"  ,  G6  on FMC
+NET "FRONT_PANEL_CLK"  LOC = "C10"; ##  "FMC_CLK0_M2C_P"  ,  H4  on FMC
+NET "FRONT_PANEL_CLK*"  LOC = “A10”; ##  "FMC_CLK0_M2C_N"  ,  H5  on FMC

circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.list

+Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat 
+   Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat (00:00:00.08)
+Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat 
+   Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat (00:00:00.01)
+Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat 
+   Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat (00:00:00.03)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcnet.dat 
+   Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcnet.dat (00:00:00.04)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialbonl.dat 
+   Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialbonl.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcprt.dat 
+   Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcprt.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialstf.dat 
+   Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialstf.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd.dat 
+   Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd_new.dat 
+   Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd_new.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.xref 
+   Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.xref (00:00:00.01)
+
+SCALD Lists Interface run on Oct 9 17:17:00 2013
+   DESIGN NAME : 'FMC_TLU_TOPLEVEL_B'
+   PACKAGING ON 02-Oct-2013 AT 09:57:38
+
+   DIRECTORIES  <none>
+   LIBRARIES  'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors'
+              'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special'
+              'bris_cds_standard' 'bris_cds_switches' 'cnconnector'
+              'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete'
+              'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als'
+              'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors'
+              'cds_special'
+   MASTER_LIBRARIES  <none>
+   MAX_ERRORS 500
+   OVERSIGHTS ON
+   SINGLE_NODE_NETS OFF
+   SUPPRESS   20
+   WARNINGS ON
+
+ No error detected
+ No oversight detected
+ No warning detected
+
+cpu time      0:00:00
+elapsed time  0:00:01
+