diff --git a/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.csv b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.csv
new file mode 100644
index 0000000000000000000000000000000000000000..1b07a39cd3a887464ccc8189dfdc7a94da062a5f
--- /dev/null
+++ b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.csv
@@ -0,0 +1,51 @@
+BUSY0* BUSY_N_I<0> H23 "FMC_LA19_N" "P7";
+BUSY1* BUSY_N_I<1> C19 "FMC_LA14_N" "A2";
+BUSY2* BUSY_N_I<2> G16 "FMC_LA12_N" "C6";
+BUSY0 BUSY_P_I<0> H22 "FMC_LA19_P" "N6";
+BUSY1 BUSY_P_I<1> C18 "FMC_LA14_P" "B2";
+BUSY2 BUSY_P_I<2> G15 "FMC_LA12_P" "D6";
+BEAM_TRIGGER_CFD*<0> CFD_DISCR_N_I<0> H38 "FMC_LA32_N" "V15";
+BEAM_TRIGGER_CFD*<1> CFD_DISCR_N_I<1> H35 "FMC_LA30_N" "V12";
+BEAM_TRIGGER_CFD*<2> CFD_DISCR_N_I<2> H32 "FMC_LA28_N" "V11";
+BEAM_TRIGGER_CFD*<3> CFD_DISCR_N_I<3> H29 "FMC_LA24_N" "V8";
+BEAM_TRIGGER_CFD<0> CFD_DISCR_P_I<0> H37 "FMC_LA32_P" "U15";
+BEAM_TRIGGER_CFD<1> CFD_DISCR_P_I<1> H34 "FMC_LA30_P" "T12";
+BEAM_TRIGGER_CFD<2> CFD_DISCR_P_I<2> H31 "FMC_LA28_P" "U11";
+BEAM_TRIGGER_CFD<3> CFD_DISCR_P_I<3> H28 "FMC_LA24_P" "U8";
+CLK1* CLK_N_I<1> C27 "FMC_LA27_N" "T11";
+CLK2* CLK_N_I<2> H8 "FMC_LA02_N" "A15";
+CLK1 CLK_P_I<1> C26 "FMC_LA27_P" "R11";
+CLK2 CLK_P_I<2> H7 "FMC_LA02_P" "C15";
+CONT0* CONT_N_I<0> G25 "FMC_LA22_N" "T7";
+CONT1* CONT_N_I<1> C23 "FMC_LA18_CC_N" "T10";
+CONT2* CONT_N_I<2> H14 "FMC_LA07_N" "E8";
+CONT0 CONT_P_I<0> G24 "FMC_LA22_P" "R7";
+CONT1 CONT_P_I<1> C22 "FMC_LA18_CC_P" "R10";
+CONT2 CONT_P_I<2> H13 "FMC_LA07_P" "E7";
+DUT_CLK0* DUT_CLK_N_I<0> H26 "FMC_LA21_N" "V4";
+DUT_CLK0 DUT_CLK_P_I<0> H25 "FMC_LA21_P" "T4";
+SPARE1* SPARE_N_I<1> G13 "FMC_LA08_N" "E11";
+SPARE2* SPARE_N_I<2> H17 "FMC_LA11_N" "A12";
+SPARE1 SPARE_P_I<1> G12 "FMC_LA08_P" "F11";
+SPARE2 SPARE_P_I<2> H16 "FMC_LA11_P" "B12";
+BEAM_TRIGGER*<0> THRESHOLD_DISCR_N_I<0> G37 "FMC_LA33_N" "N9";
+BEAM_TRIGGER*<1> THRESHOLD_DISCR_N_I<1> G34 "FMC_LA31_N" "V6";
+BEAM_TRIGGER*<2> THRESHOLD_DISCR_N_I<2> G31 "FMC_LA29_N" "N8";
+BEAM_TRIGGER*<3> THRESHOLD_DISCR_N_I<3> G28 "FMC_LA25_N" "N11";
+BEAM_TRIGGER<0> THRESHOLD_DISCR_P_I<0> G36 "FMC_LA33_P" "M10";
+BEAM_TRIGGER<1> THRESHOLD_DISCR_P_I<1> G33 "FMC_LA31_P" "T6";
+BEAM_TRIGGER<2> THRESHOLD_DISCR_P_I<2> G30 "FMC_LA29_P" "M8";
+BEAM_TRIGGER<3> THRESHOLD_DISCR_P_I<3> G27 "FMC_LA25_P" "M11";
+TRIG0* TRIG_N_I<0> G22 "FMC_LA20_N" "P8";
+TRIG1* TRIG_N_I<1> G10 "FMC_LA03_N" "A13";
+TRIG2* TRIG_N_I<2> G19 "FMC_LA16_N" "A7";
+TRIG0 TRIG_P_I<0> G21 "FMC_LA20_P" "N7";
+TRIG1 TRIG_P_I<1> G9 "FMC_LA03_P" "C13";
+TRIG2 TRIG_P_I<2> G18 "FMC_LA16_P" "C7";
+HDMI_POWER_ENABLE1 HDMI_POWER_ENABLE1 H10 "FMC_LA04_P" "B16";
+HDMI_POWER_ENABLE2 HDMI_POWER_ENABLE2 H20 "FMC_LA15_N" "F9";
+FMC_LA*<2> FMC_LA*<2> G3 "FMC_CLK1_M2C_N" "V9";
+FMC_LA<2> FMC_LA<2> G2 "FMC_CLK1_M2C_P" "T9";
+FMC_LA<29> FMC_LA<29> G6 "FMC_LA00_CC_P" "D9";
+FRONT_PANEL_CLK FRONT_PANEL_CLK H4 "FMC_CLK0_M2C_P" "C10";
+FRONT_PANEL_CLK* FRONT_PANEL_CLK* H5 "FMC_CLK0_M2C_N" “A10â€;
diff --git a/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.ucf b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.ucf
new file mode 100644
index 0000000000000000000000000000000000000000..c20ae8a6a7b9141347dd9395bd983e1d73683aec
--- /dev/null
+++ b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.ucf
@@ -0,0 +1,51 @@
+NET "BUSY_N_I<0>" LOC = "P7"; ## "FMC_LA19_N" , H23 on FMC
+NET "BUSY_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
+NET "BUSY_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
+NET "BUSY_P_I<0>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
+NET "BUSY_P_I<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
+NET "BUSY_P_I<2>" LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
+NET "CFD_DISCR_N_I<0>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
+NET "CFD_DISCR_N_I<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
+NET "CFD_DISCR_N_I<2>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
+NET "CFD_DISCR_N_I<3>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC
+NET "CFD_DISCR_P_I<0>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
+NET "CFD_DISCR_P_I<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
+NET "CFD_DISCR_P_I<2>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
+NET "CFD_DISCR_P_I<3>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC
+NET "CLK_N_I<1>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
+NET "CLK_N_I<2>" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
+NET "CLK_P_I<1>" LOC = "R11"; ## "FMC_LA27_P" , C26 on FMC
+NET "CLK_P_I<2>" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
+NET "CONT_N_I<0>" LOC = "T7"; ## "FMC_LA22_N" , G25 on FMC
+NET "CONT_N_I<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
+NET "CONT_N_I<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
+NET "CONT_P_I<0>" LOC = "R7"; ## "FMC_LA22_P" , G24 on FMC
+NET "CONT_P_I<1>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
+NET "CONT_P_I<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
+NET "DUT_CLK_N_I<0>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
+NET "DUT_CLK_P_I<0>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC
+NET "SPARE_N_I<1>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC
+NET "SPARE_N_I<2>" LOC = "A12"; ## "FMC_LA11_N" , H17 on FMC
+NET "SPARE_P_I<1>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC
+NET "SPARE_P_I<2>" LOC = "B12"; ## "FMC_LA11_P" , H16 on FMC
+NET "THRESHOLD_DISCR_N_I<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC
+NET "THRESHOLD_DISCR_N_I<1>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC
+NET "THRESHOLD_DISCR_N_I<2>" LOC = "N8"; ## "FMC_LA29_N" , G31 on FMC
+NET "THRESHOLD_DISCR_N_I<3>" LOC = "N11"; ## "FMC_LA25_N" , G28 on FMC
+NET "THRESHOLD_DISCR_P_I<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC
+NET "THRESHOLD_DISCR_P_I<1>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC
+NET "THRESHOLD_DISCR_P_I<2>" LOC = "M8"; ## "FMC_LA29_P" , G30 on FMC
+NET "THRESHOLD_DISCR_P_I<3>" LOC = "M11"; ## "FMC_LA25_P" , G27 on FMC
+NET "TRIG_N_I<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
+NET "TRIG_N_I<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
+NET "TRIG_N_I<2>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
+NET "TRIG_P_I<0>" LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
+NET "TRIG_P_I<1>" LOC = "C13"; ## "FMC_LA03_P" , G9 on FMC
+NET "TRIG_P_I<2>" LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
+NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
+NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
+NET "FMC_LA*<2>" LOC = "V9"; ## "FMC_CLK1_M2C_N" , G3 on FMC
+NET "FMC_LA<2>" LOC = "T9"; ## "FMC_CLK1_M2C_P" , G2 on FMC
+NET "FMC_LA<29>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
+NET "FRONT_PANEL_CLK" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC
+NET "FRONT_PANEL_CLK*" LOC = “A10â€; ## "FMC_CLK0_M2C_N" , H5 on FMC
diff --git a/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.xlsx b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.xlsx
new file mode 100644
index 0000000000000000000000000000000000000000..cf0a1568c41504c99e67850f3fd2d231b1852d9d
Binary files /dev/null and b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/nets_mapped_to_fpga_ucf.xlsx differ
diff --git a/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.list b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.list
new file mode 100644
index 0000000000000000000000000000000000000000..cac224511ade1f4cafc917213180d74ba564ad2e
--- /dev/null
+++ b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.list
@@ -0,0 +1,47 @@
+Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat
+ Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstchip.dat (00:00:00.08)
+Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat
+ Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxprt.dat (00:00:00.01)
+Starting to read /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat
+ Finished reading /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/pstxnet.dat (00:00:00.03)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcnet.dat
+ Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcnet.dat (00:00:00.04)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialbonl.dat
+ Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialbonl.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcprt.dat
+ Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialcprt.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialstf.dat
+ Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialstf.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd.dat
+ Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd_new.dat
+ Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/dialpgnd_new.dat (00:00:00.01)
+Starting to generate /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.xref
+ Finished generating /projects/HEP_Instrumentation/cad/designs/fmc-mtlu/trunk/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.xref (00:00:00.01)
+
+SCALD Lists Interface run on Oct 9 17:17:00 2013
+ DESIGN NAME : 'FMC_TLU_TOPLEVEL_B'
+ PACKAGING ON 02-Oct-2013 AT 09:57:38
+
+ DIRECTORIES <none>
+ LIBRARIES 'fmc_tlu_v1_lib' 'bris_cds_analogue' 'bris_cds_connectors'
+ 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_special'
+ 'bris_cds_standard' 'bris_cds_switches' 'cnconnector'
+ 'cninterface' 'cnpower' 'cnlinear' 'cnpassive' 'cndiscrete'
+ 'standard' 'cds_analogue' 'cn100e' 'cn74lv' 'cn74tiac' 'cn75als'
+ 'cncmos' 'cnfast' 'cnmemory' 'uob_hep_pc036a_lib' 'cds_connectors'
+ 'cds_special'
+ MASTER_LIBRARIES <none>
+ MAX_ERRORS 500
+ OVERSIGHTS ON
+ SINGLE_NODE_NETS OFF
+ SUPPRESS 20
+ WARNINGS ON
+
+ No error detected
+ No oversight detected
+ No warning detected
+
+cpu time 0:00:00
+elapsed time 0:00:01
+
diff --git a/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.xref b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.xref
new file mode 100644
index 0000000000000000000000000000000000000000..c91b66f74871a3f2f4bbaace76f990840477f534
--- /dev/null
+++ b/circuit_board/Cadence/worklib/fmc_tlu_toplevel_b/packaged/scald.xref
@@ -0,0 +1,2598 @@
+FILE_TYPE=CROSS_REFERENCE;
+ROOT_DRAWING='FMC_TLU_TOPLEVEL_B';
+RUN_TIME='Oct 9 17:17:00 2013';
+PROGRAM_VERSION='15.50-p001';
+**** Part Type '24AA025E48_SOIC' ('24AA025E48') ****
+**** Part Type 'AD5665R_TSSOP' ('AD5665RBRUZ-1-GND=GND_SIGNAL,VA') ****
+**** Part Type 'CON160P_40CDGH' ('ASP-134606-01') ****
+**** Part Type 'CAPCERSMDCL2_0603' ('CAPCERSMDCL2_0603-1.0UF,6.3V') ****
+**** Part Type 'CAPCERSMDCL2_0603' ('CAPCERSMDCL2_0603-100NF,16V') ****
+**** Part Type 'CAPCERSMDCL2_0603' ('CAPCERSMDCL2_0603-10NF,50V') ****
+**** Part Type 'CAPCERSMDCL2_0603' ('CAPCERSMDCL2_0603-1UF,16V') ****
+**** Part Type 'CAPCERSMDCL2_0805' ('CAPCERSMDCL2_0805-4.7UF,10V') ****
+**** Part Type 'CAPCERSMDCL2_1210' ('CAPCERSMDCL2_1210-22UF,16V') ****
+**** Part Type 'CAPCERSMDCL2_1210' ('CAPCERSMDCL2_1210-4.7UF,50V') ****
+**** Part Type 'CON16P' ('CON16P-HW8_08G_SM') ****
+**** Part Type 'CON19P' ('CON19P-MHDMI-19-02-H-TH-L-TR-GA') ****
+**** Part Type 'CON19P' ('CON19P-MHDMI-19-02-H-TH-L-TR-GB') ****
+**** Part Type 'CON8P' ('CON8P-44661-1011-GND=FRAME') ****
+**** Part Type 'FERRITE_SMD' ('FERRITE_SMD-7427921,WURTH') ****
+**** Part Type 'FERRITE_SMD' ('FERRITE_SMD-BLM41P800S,MURATA') ****
+**** Part Type 'FMC_TLU_TOPLEVEL_B' ('FMC_TLU_TOPLEVEL_B') ****
+
+PART CROSS REFERENCE (forward interface)
+
+CAPCERSMDCL2_0603 I90 C1 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I123 C2 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+CAPCERSMDCL2_0603 I123 C3 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+CAPCERSMDCL2_0603 I123 C4 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+CAPCERSMDCL2_0603 I123 C5 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+CAPCERSMDCL2_0603 I51 C6 [CAPCERSMDCL2_0603-1UF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0805 I58 C7 [CAPCERSMDCL2_0805-4.7UF,10V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0805 I56 C8 [CAPCERSMDCL2_0805-4.7UF,10V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I79 C9 [CAPCERSMDCL2_1210-4.7UF,50V]
+ 2 P12V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P12V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0805 I52 C10 [CAPCERSMDCL2_0805-4.7UF,10V]
+ 2 P5V7_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):P5V7
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I78 C11 [CAPCERSMDCL2_0603-10NF,50V]
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I78 C12 [CAPCERSMDCL2_0603-10NF,50V]
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I78 C13 [CAPCERSMDCL2_0603-10NF,50V]
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I78 C14 [CAPCERSMDCL2_0603-10NF,50V]
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I44 C15 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I44 C16 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I44 C17 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I44 C18 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I151 C19 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I151 C20 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I151 C21 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I151 C22 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0805 I54 C23 [CAPCERSMDCL2_0805-4.7UF,10V]
+ 2 M5V7_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):M5V7
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I150 C24 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I150 C25 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I150 C26 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I150 C27 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I81 C28 [CAPCERSMDCL2_1210-4.7UF,50V]
+ 2 VIN_FILTERED_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ 1 UNNAMED_1_CAPCERSMDCL2_I81_A_6 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_CAPCERSMDCL2_I81_A
+
+CAPCERSMDCL2_0603 I73 C29 [CAPCERSMDCL2_0603-1UF,16V]
+ 2 P3V3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I39 C30 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I39 C31 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I39 C32 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I39 C33 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I72 C34 [CAPCERSMDCL2_1210-4.7UF,50V]
+ 2 VIN_FILTERED_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I88 C35 [CAPCERSMDCL2_1210-22UF,16V]
+ 2 VM2<0>_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I47 C36 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I47 C37 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I47 C38 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I47 C39 [CAPCERSMDCL2_0603-1.0UF,6.3V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I50 C40 [CAPCERSMDCL2_0603-1UF,16V]
+ 2 P3V3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I142 C41 [CAPCERSMDCL2_1210-4.7UF,50V]
+ 2 VIN_FILTERED_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I53 C42 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P3V3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I83 C43 [CAPCERSMDCL2_1210-4.7UF,50V]
+ 2 VIN_FILTERED_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I144 C44 [CAPCERSMDCL2_1210-4.7UF,50V]
+ 2 VIN_FILTERED_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_1210 I89 C45 [CAPCERSMDCL2_1210-22UF,16V]
+ 2 VP1<0>_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I42 C46 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 UNNAMED_4_CAPCERSMDCL2_I42_B B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I42_B
+ 1 GND_HDMI2 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_HDMI2
+
+CAPCERSMDCL2_0603 I41 C47 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 UNNAMED_4_CAPCERSMDCL2_I41_B B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I41_B
+ 1 GND_HDMI2 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_HDMI2
+
+CAPCERSMDCL2_0603 I9 C48 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 UNNAMED_4_CAPCERSMDCL2_I9_B B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I9_B
+ 1 GND_HDMI1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_HDMI1
+
+CAPCERSMDCL2_0603 I8 C49 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 UNNAMED_4_CAPCERSMDCL2_I8_B B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I8_B
+ 1 GND_HDMI1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_HDMI1
+
+CAPCERSMDCL2_0603 I60 C50 [CAPCERSMDCL2_0603-100NF,16V]
+ 1 P2V5 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I56 C51 [CAPCERSMDCL2_0603-100NF,16V]
+ 1 P2V5 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I19 C52 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 UNNAMED_4_CAPCERSMDCL2_I19_B B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I19_B
+ 1 FRAME A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRAME
+
+CAPCERSMDCL2_0603 I22 C53 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 UNNAMED_4_CAPCERSMDCL2_I22_B B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I22_B
+ 1 FRAME A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRAME
+
+CAPCERSMDCL2_0603 I9 C54 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I9 C55 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I9 C56 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P2V5 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I40 C57 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I41 C58 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I40 C59 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I41 C60 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I40 C61 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I41 C62 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I40 C63 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I41 C64 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I52 C65 [CAPCERSMDCL2_0603-1UF,16V]
+ 1 M5V A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I43 C66 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I43 C67 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I43 C68 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I43 C69 [CAPCERSMDCL2_0603-100NF,16V]
+ 2 M5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I11 C70 [CAPCERSMDCL2_0603-100NF,16V]
+ 1 P3V3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CAPCERSMDCL2_0603 I66 C71 [CAPCERSMDCL2_0603-1UF,16V]
+ 2 VREF B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+USBLC6-2_SOT23 I49 D1 [USBLC6-2SC6]
+ 6 TRIG2* I/O1<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG2*
+ 4 TRIG2 I/O2<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG2
+ 5 P2V5 VBUS @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 2 GND_SIGNAL GND @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 1 CTRIG2* I/O1<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG2*
+ 3 CTRIG2 I/O2<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG2
+
+USBLC6-2_SOT23 I33 D2 [USBLC6-2SC6]
+ 6 TRIG1* I/O1<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG1*
+ 4 TRIG1 I/O2<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG1
+ 5 P2V5 VBUS @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 2 GND_SIGNAL GND @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 1 CTRIG1* I/O1<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1*
+ 3 CTRIG1 I/O2<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1
+
+USBLC6-2_SOT23 I92 D3 [USBLC6-2SC6]
+ 3 UNNAMED_1_PLEMO2CI_I7_B I/O2<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_PLEMO2CI_I7_B
+ 1 UNNAMED_1_PLEMO2CI_I7_A I/O1<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_PLEMO2CI_I7_A
+ 5 P2V5 VBUS @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 2 GND_SIGNAL GND @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 4 FRONT_PANEL_CLK* I/O2<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRONT_PANEL_CLK*
+ 6 FRONT_PANEL_CLK I/O1<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRONT_PANEL_CLK
+
+DIODE_DUAL_SERIES_A1-C2-AC3 I120 D4 [HBAT-540C]
+ 2 P5V C @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 3 IN<3> AC @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<3>
+
+DIODE_DUAL_SERIES_A1-C2-AC3 I120 D5 [HBAT-540C]
+ 2 P5V C @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 3 IN<2> AC @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<2>
+
+DIODE_DUAL_SERIES_A1-C2-AC3 I120 D6 [HBAT-540C]
+ 2 P5V C @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 3 IN<1> AC @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<1>
+
+DIODE_DUAL_SERIES_A1-C2-AC3 I120 D7 [HBAT-540C]
+ 2 P5V C @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 1 M5V A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 3 IN<0> AC @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<0>
+
+74LVC1G07_SC70 I40 IC1 [SN74LVC1G07DCK-GND=GND_SIGNAL,A]
+ 4 UNNAMED_4_74LVC1G07_I40_Y Y @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I40_Y
+ 2 HDMI_POWER_ENABLE2 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):HDMI_POWER_ENABLE2
+
+74LVC1G07_SC70 I28 IC2 [SN74LVC1G07DCK-GND=GND_SIGNAL,A]
+ 4 UNNAMED_4_74LVC1G07_I28_Y Y @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I28_Y
+ 2 HDMI_POWER_ENABLE1 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):HDMI_POWER_ENABLE1
+
+OPA4277_SOIC I22 IC3 [OPA4277UA]
+ 14 VTHRESH<1> OUT<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<1>
+ 13 UNNAMED_1_OPA4277_I22_MIN_3 MIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I32@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ 12 UNNAMED_1_AD5665R_I63_VOUTB PIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTB
+ 4 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 11 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+OPA4277_SOIC I22 IC3 [OPA4277UA]
+ 8 VTHRESH<2> OUT<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<2>
+ 9 UNNAMED_1_OPA4277_I22_MIN_2 MIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I31@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ 10 UNNAMED_1_AD5665R_I63_VOUTC PIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTC
+ 4 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 11 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+OPA4277_SOIC I22 IC3 [OPA4277UA]
+ 7 VTHRESH<3> OUT<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<3>
+ 6 UNNAMED_1_OPA4277_I22_MIN_1 MIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I30@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ 5 UNNAMED_1_AD5665R_I63_VOUTD PIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTD
+ 4 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 11 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+OPA4277_SOIC I22 IC3 [OPA4277UA]
+ 1 VTHRESH<0> OUT<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<0>
+ 2 UNNAMED_1_OPA4277_I22_MIN MIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I29@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ 3 UNNAMED_1_AD5665R_I63_VOUTA PIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTA
+ 4 P5V V+ @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 11 M5V V- @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+
+MAX9601_TSSOP I71 IC4 []
+ 13 UNNAMED_1_MAX9601_I71_HYS_1 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 11 UNNAMED_1_CAPCERSMDCL2_I78_B_1 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 14 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 16 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 18 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 12 IN<3> IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<3>
+ 17 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 20 BEAM_TRIGGER<3> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<3>
+ 19 BEAM_TRIGGER*<3> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<3>
+
+MAX9601_TSSOP I1 IC4 []
+ 9 UNNAMED_1_MAX9601_I1_IN_1_1 IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 10 UNNAMED_1_MAX9601_I1_IN_1 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 8 UNNAMED_1_MAX9601_I1_HYS_1 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 14 P5V VCC<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V VCC<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 18 P2V5 VCCO_<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 VCCO_<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 5 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V VEE<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V VEE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 4 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 1 BEAM_TRIGGER_CFD<3> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<3>
+ 2 BEAM_TRIGGER_CFD*<3> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<3>
+
+MAX9601_TSSOP I71 IC5 []
+ 13 UNNAMED_1_MAX9601_I71_HYS_2 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 11 UNNAMED_1_CAPCERSMDCL2_I78_B_2 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 14 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 16 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 18 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 12 IN<2> IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<2>
+ 17 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 20 BEAM_TRIGGER<2> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<2>
+ 19 BEAM_TRIGGER*<2> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<2>
+
+MAX9601_TSSOP I1 IC5 []
+ 10 UNNAMED_1_MAX9601_I1_IN_2 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 9 UNNAMED_1_MAX9601_I1_IN_1_2 IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 8 UNNAMED_1_MAX9601_I1_HYS_2 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 14 P5V VCC<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V VCC<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 18 P2V5 VCCO_<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 VCCO_<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 5 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V VEE<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V VEE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 4 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 1 BEAM_TRIGGER_CFD<2> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<2>
+ 2 BEAM_TRIGGER_CFD*<2> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<2>
+
+MAX9601_TSSOP I71 IC6 []
+ 13 UNNAMED_1_MAX9601_I71_HYS_3 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 11 UNNAMED_1_CAPCERSMDCL2_I78_B_3 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 14 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 16 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 18 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 12 IN<1> IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<1>
+ 17 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 20 BEAM_TRIGGER<1> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<1>
+ 19 BEAM_TRIGGER*<1> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<1>
+
+MAX9601_TSSOP I1 IC6 []
+ 10 UNNAMED_1_MAX9601_I1_IN_3 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 9 UNNAMED_1_MAX9601_I1_IN_1_3 IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 8 UNNAMED_1_MAX9601_I1_HYS_3 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 14 P5V VCC<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V VCC<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 18 P2V5 VCCO_<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 VCCO_<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 5 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V VEE<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V VEE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 4 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 1 BEAM_TRIGGER_CFD<1> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<1>
+ 2 BEAM_TRIGGER_CFD*<1> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<1>
+
+MAX9601_TSSOP I71 IC7 []
+ 13 UNNAMED_1_MAX9601_I71_HYS_4 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 11 UNNAMED_1_CAPCERSMDCL2_I78_B_4 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ 14 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 16 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 18 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 12 IN<0> IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<0>
+ 17 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 20 BEAM_TRIGGER<0> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<0>
+ 19 BEAM_TRIGGER*<0> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<0>
+
+MAX9601_TSSOP I1 IC7 []
+ 10 UNNAMED_1_MAX9601_I1_IN_4 IN+<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 9 UNNAMED_1_MAX9601_I1_IN_1_4 IN-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 8 UNNAMED_1_MAX9601_I1_HYS_4 HYS<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 14 P5V VCC<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 7 P5V VCC<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 18 P2V5 VCCO_<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 3 P2V5 VCCO_<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 5 P2V5 LE*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ 15 M5V VEE<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 6 M5V VEE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 4 GND_SIGNAL LE<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 1 BEAM_TRIGGER_CFD<0> Q<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<0>
+ 2 BEAM_TRIGGER_CFD*<0> Q*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<0>
+
+AD5665R_TSSOP I63 IC8 [AD5665RBRUZ-1-GND=GND_SIGNAL,VA]
+ 7 VREF VREFIN/VREFOUT @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ 10 UNNAMED_1_AD5665R_I63_VOUTD VOUTD @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTD
+ 5 UNNAMED_1_AD5665R_I63_VOUTC VOUTC @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTC
+ 11 UNNAMED_1_AD5665R_I63_VOUTB VOUTB @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTB
+ 4 UNNAMED_1_AD5665R_I63_VOUTA VOUTA @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTA
+ 13 SDA SDA @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SDA
+ 14 SCL SCL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SCL
+ 6 P3V3 POR @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 9 P3V3 CLR* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 1 GND_SIGNAL LDAC* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 8 GND_SIGNAL ADDR2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 GND_SIGNAL ADDR1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+24AA025E48_SOIC I8 IC9 [24AA025E48]
+ 3 UNNAMED_1_24AA025E48_I8_A2 A2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A2
+ 2 UNNAMED_1_24AA025E48_I8_A1 A1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A1
+ 1 UNNAMED_1_24AA025E48_I8_A0 A0 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A0
+ 5 SDA SDA @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SDA
+ 6 SCL SCL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SCL
+ 8 P3V3 VCC @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 4 GND_SIGNAL VSS @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+CON19P I2 J1 [CON19P-MHDMI-19-02-H-TH-L-TR-GA]
+ 14 UNNAMED_4_CON19P_I2_A A<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CON19P_I2_A
+ 12 SPARE1* A<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1*
+ 10 SPARE1 A<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1
+ 19 NC A<18> NC
+ 18 NC A<17> NC
+ 13 NC A<12> NC
+ 17 GND_SIGNAL A<16> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 11 GND_SIGNAL A<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 8 GND_SIGNAL A<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 5 GND_SIGNAL A<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 GND_SIGNAL A<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 16 CTRIG1* A<15> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1*
+ 15 CTRIG1 A<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1
+ 6 CONT1* A<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1*
+ 4 CONT1 A<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1
+ 1 CLK1* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1*
+ 3 CLK1 A<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1
+ 9 BUSY1* A<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1*
+ 7 BUSY1 A<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1
+
+CON19P I3 J2 [CON19P-MHDMI-19-02-H-TH-L-TR-GB]
+ 14 UNNAMED_4_CON19P_I3_A A<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CON19P_I3_A
+ 12 SPARE2* A<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2*
+ 10 SPARE2 A<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2
+ 19 NC A<18> NC
+ 18 NC A<17> NC
+ 13 NC A<12> NC
+ 17 GND_SIGNAL A<16> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 11 GND_SIGNAL A<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 8 GND_SIGNAL A<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 5 GND_SIGNAL A<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 GND_SIGNAL A<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 16 CTRIG2* A<15> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG2*
+ 15 CTRIG2 A<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG2
+ 6 CONT2* A<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2*
+ 4 CONT2 A<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2
+ 1 CLK2* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2*
+ 3 CLK2 A<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2
+ 9 BUSY2* A<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2*
+ 7 BUSY2 A<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2
+
+CON8P I78 J3 [CON8P-44661-1011-GND=FRAME]
+ 7 TRIG0* A<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0*
+ 8 TRIG0 A<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0
+ 1 DUT_CLK0* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0*
+ 2 DUT_CLK0 A<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0
+ 4 CONT0* A<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0*
+ 5 CONT0 A<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0
+ 3 BUSY0* A<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0*
+ 6 BUSY0 A<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0
+
+CON160P_40CDGH I1 J4 [ASP-134606-01]
+ H1 NC H<1> NC
+ G19 TRIG2* G<19> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG2*
+ G18 TRIG2 G<18> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG2
+ G10 TRIG1* G<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG1*
+ G9 TRIG1 G<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG1
+ G22 TRIG0* G<22> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0*
+ G21 TRIG0 G<21> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0
+ H17 SPARE2* H<17> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2*
+ H16 SPARE2 H<16> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2
+ G13 SPARE1* G<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1*
+ G12 SPARE1 G<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1
+ H40 P2V5 H<40> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ G39 P2V5 G<39> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ H20 HDMI_POWER_ENABLE2 H<20> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):HDMI_POWER_ENABLE2
+ H10 HDMI_POWER_ENABLE1 H<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):HDMI_POWER_ENABLE1
+ H39 GND_SIGNAL H<39> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H36 GND_SIGNAL H<36> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H33 GND_SIGNAL H<33> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H30 GND_SIGNAL H<30> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H27 GND_SIGNAL H<27> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H24 GND_SIGNAL H<24> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H21 GND_SIGNAL H<21> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H18 GND_SIGNAL H<18> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H15 GND_SIGNAL H<15> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H12 GND_SIGNAL H<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H9 GND_SIGNAL H<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H6 GND_SIGNAL H<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H3 GND_SIGNAL H<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G40 GND_SIGNAL G<40> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G38 GND_SIGNAL G<38> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G35 GND_SIGNAL G<35> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G32 GND_SIGNAL G<32> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G29 GND_SIGNAL G<29> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G26 GND_SIGNAL G<26> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G23 GND_SIGNAL G<23> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G20 GND_SIGNAL G<20> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G17 GND_SIGNAL G<17> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G14 GND_SIGNAL G<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G11 GND_SIGNAL G<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G8 GND_SIGNAL G<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G5 GND_SIGNAL G<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G4 GND_SIGNAL G<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G1 GND_SIGNAL G<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H5 FRONT_PANEL_CLK* H<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRONT_PANEL_CLK*
+ H4 FRONT_PANEL_CLK H<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRONT_PANEL_CLK
+ H2 NC H<2> NC
+ G2 FMC_LA<2> G<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK_IO_1
+ G6 FMC_LA<29> G<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GPIO_CLK
+ H19 NC H<19> NC
+ H11 NC H<11> NC
+ G3 FMC_LA*<2> G<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK_IO_2
+ G7 NC G<7> NC
+ H26 DUT_CLK0* H<26> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0*
+ H25 DUT_CLK0 H<25> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0
+ H14 CONT2* H<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2*
+ H13 CONT2 H<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2
+ G25 CONT0* G<25> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0*
+ G24 CONT0 G<24> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0
+ H8 CLK2* H<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2*
+ H7 CLK2 H<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2
+ G16 BUSY2* G<16> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2*
+ G15 BUSY2 G<15> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2
+ H23 BUSY0* H<23> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0*
+ H22 BUSY0 H<22> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0
+ H28 BEAM_TRIGGER_CFD<3> H<28> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<3>
+ H31 BEAM_TRIGGER_CFD<2> H<31> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<2>
+ H34 BEAM_TRIGGER_CFD<1> H<34> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<1>
+ H37 BEAM_TRIGGER_CFD<0> H<37> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<0>
+ H29 BEAM_TRIGGER_CFD*<3> H<29> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<3>
+ H32 BEAM_TRIGGER_CFD*<2> H<32> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<2>
+ H35 BEAM_TRIGGER_CFD*<1> H<35> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<1>
+ H38 BEAM_TRIGGER_CFD*<0> H<38> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<0>
+ G27 BEAM_TRIGGER<3> G<27> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<3>
+ G30 BEAM_TRIGGER<2> G<30> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<2>
+ G33 BEAM_TRIGGER<1> G<33> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<1>
+ G36 BEAM_TRIGGER<0> G<36> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<0>
+ G28 BEAM_TRIGGER*<3> G<28> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<3>
+ G31 BEAM_TRIGGER*<2> G<31> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<2>
+ G34 BEAM_TRIGGER*<1> G<34> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<1>
+ G37 BEAM_TRIGGER*<0> G<37> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<0>
+
+CON160P_40CDGH I2 J4 [ASP-134606-01]
+ D34 NC D<34> NC
+ C31 SDA C<31> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SDA
+ C30 SCL C<30> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SCL
+ D40 P3V3 D<40> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ D38 P3V3 D<38> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ D36 P3V3 D<36> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ D32 P3V3 D<32> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ C39 P3V3 C<39> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ C37 P12V C<37> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P12V
+ C35 P12V C<35> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P12V
+ D39 GND_SIGNAL D<39> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D37 GND_SIGNAL D<37> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D28 GND_SIGNAL D<28> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D25 GND_SIGNAL D<25> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D22 GND_SIGNAL D<22> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D19 GND_SIGNAL D<19> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D16 GND_SIGNAL D<16> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D13 GND_SIGNAL D<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D10 GND_SIGNAL D<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D7 GND_SIGNAL D<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D6 GND_SIGNAL D<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D3 GND_SIGNAL D<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D2 GND_SIGNAL D<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C40 GND_SIGNAL C<40> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C38 GND_SIGNAL C<38> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C36 GND_SIGNAL C<36> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C33 GND_SIGNAL C<33> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C32 GND_SIGNAL C<32> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C29 GND_SIGNAL C<29> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C28 GND_SIGNAL C<28> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C25 GND_SIGNAL C<25> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C24 GND_SIGNAL C<24> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C21 GND_SIGNAL C<21> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C20 GND_SIGNAL C<20> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C17 GND_SIGNAL C<17> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C16 GND_SIGNAL C<16> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C13 GND_SIGNAL C<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C12 GND_SIGNAL C<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C9 GND_SIGNAL C<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C8 GND_SIGNAL C<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C5 GND_SIGNAL C<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C4 GND_SIGNAL C<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C1 GND_SIGNAL C<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ D5 NC D<5> NC
+ D4 NC D<4> NC
+ D35 NC D<35> NC
+ C34 NC C<34> NC
+ D30 NC D<30> NC
+ D33 NC D<33> NC
+ D31 NC D<31> NC
+ D29 NC D<29> NC
+ D1 NC D<1> NC
+ D14 NC D<14> NC
+ C10 NC C<10> NC
+ D11 NC D<11> NC
+ D26 NC D<26> NC
+ D23 NC D<23> NC
+ D8 NC D<8> NC
+ D20 NC D<20> NC
+ D17 NC D<17> NC
+ C14 NC C<14> NC
+ D15 NC D<15> NC
+ C11 NC C<11> NC
+ D12 NC D<12> NC
+ D27 NC D<27> NC
+ D24 NC D<24> NC
+ D9 NC D<9> NC
+ D21 NC D<21> NC
+ D18 NC D<18> NC
+ C15 NC C<15> NC
+ C7 NC C<7> NC
+ C6 NC C<6> NC
+ C3 NC C<3> NC
+ C2 NC C<2> NC
+ C23 CONT1* C<23> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1*
+ C22 CONT1 C<22> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1
+ C27 CLK1* C<27> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1*
+ C26 CLK1 C<26> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1
+ C19 BUSY1* C<19> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1*
+ C18 BUSY1 C<18> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1
+
+FERRITE_SMD I66 L1 [FERRITE_SMD-BLM41P800S,MURATA]
+ 2 VIN_FILTERED_6 B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ 1 P12V A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P12V
+
+FERRITE_SMD I44 L2 [FERRITE_SMD-7427921,WURTH]
+ 1 VM2<0>_6 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ 2 M5V7_6 B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):M5V7
+
+FERRITE_SMD I42 L3 [FERRITE_SMD-7427921,WURTH]
+ 1 VP1<0>_6 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ 2 P5V7_6 B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):P5V7
+
+CON16P I93 PL1 [CON16P-HW8_08G_SM]
+ 12 SDA A<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SDA
+ 14 SCL A<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SCL
+ 15 P5V A<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 2 P3V3 A<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 1 P3V3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 10 NC A<9> NC
+ 16 M5V A<15> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 13 GND_SIGNAL A<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 11 GND_SIGNAL A<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 9 GND_SIGNAL A<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 7 GND_SIGNAL A<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 5 GND_SIGNAL A<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 3 GND_SIGNAL A<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 4 FMC_LA<2> A<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK_IO_1
+ 6 FMC_LA<29> A<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GPIO_CLK
+ 8 FMC_LA*<2> A<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK_IO_2
+
+PLEMO2CI I7 PX1 [PLEMO2CI-PLEMO2-00B-GND=GND_SIA]
+ 2 UNNAMED_1_PLEMO2CI_I7_B B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_PLEMO2CI_I7_B
+ 1 UNNAMED_1_PLEMO2CI_I7_A A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_PLEMO2CI_I7_A
+
+PCOAX I54 PX2 [PCOAX-PLEMO00C-GND=GND_SIGNAL]
+ 1 IN<3> A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<3>
+
+PCOAX I53 PX3 [PCOAX-PLEMO00C-GND=GND_SIGNAL]
+ 1 IN<2> A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<2>
+
+PCOAX I52 PX4 [PCOAX-PLEMO00C-GND=GND_SIGNAL]
+ 1 IN<1> A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<1>
+
+PCOAX I51 PX5 [PCOAX-PLEMO00C-GND=GND_SIGNAL]
+ 1 IN<0> A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<0>
+
+PCOAXSMD I168 PX6 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_1 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+
+PCOAXSMD I168 PX7 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_2 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+
+PCOAXSMD I168 PX8 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_3 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+
+PCOAXSMD I168 PX9 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_4 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+
+PCOAXSMD I169 PX10 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_MAX9601_I1_IN_1_1 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+
+PCOAXSMD I169 PX11 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_MAX9601_I1_IN_1_2 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+
+PCOAXSMD I169 PX12 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_MAX9601_I1_IN_1_3 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+
+PCOAXSMD I169 PX13 [PCOAXSMD-UFL_R_SMT-GND=GND_SIGA]
+ 1 UNNAMED_1_MAX9601_I1_IN_1_4 A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+
+RSMD0603_1/10W I29 R1 [RSMD0603_1/10W-1K,1%]
+ 1 UNNAMED_4_74LVC1G07_I28_Y A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I28_Y
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+
+RSMD0603_1/10W I44 R2 [RSMD0603_1/10W-1K,1%]
+ 1 UNNAMED_4_74LVC1G07_I40_Y A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I40_Y
+ 2 P5V B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+
+RSMD0603_1/10W I24 R3 [RSMD0603_1/10W-10K,1%]
+ 1 VREF A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ 2 UNNAMED_1_OPA4277_I22_MIN_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I32@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I24 R4 [RSMD0603_1/10W-10K,1%]
+ 1 VREF A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ 2 UNNAMED_1_OPA4277_I22_MIN_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I31@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I23 R5 [RSMD0603_1/10W-10K,1%]
+ 2 VTHRESH<2> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<2>
+ 1 UNNAMED_1_OPA4277_I22_MIN_2 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I31@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I23 R6 [RSMD0603_1/10W-10K,1%]
+ 2 VTHRESH<1> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<1>
+ 1 UNNAMED_1_OPA4277_I22_MIN_3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I32@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I79 R7 [RSMD0603_1/10W-100,1%]
+ 1 VTHRESH<3> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<3>
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+RSMD0603_1/10W I79 R8 [RSMD0603_1/10W-100,1%]
+ 1 VTHRESH<2> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<2>
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+RSMD0603_1/10W I79 R9 [RSMD0603_1/10W-100,1%]
+ 1 VTHRESH<1> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<1>
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+RSMD0603_1/10W I79 R10 [RSMD0603_1/10W-100,1%]
+ 1 VTHRESH<0> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<0>
+ 2 UNNAMED_1_CAPCERSMDCL2_I78_B_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+RSMD0805_125MW I94 R11 [RSMD0805_125MW-12,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 IN<3> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<3>
+
+RSMD0805_125MW I94 R12 [RSMD0805_125MW-12,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_2 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 IN<2> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<2>
+
+RSMD0805_125MW I94 R13 [RSMD0805_125MW-12,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 IN<1> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<1>
+
+RSMD0805_125MW I94 R14 [RSMD0805_125MW-12,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_4 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 IN<0> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<0>
+
+RSMD0603_1/10W I92 R15 [RSMD0603_1/10W-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I92 R16 [RSMD0603_1/10W-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I92 R17 [RSMD0603_1/10W-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I92 R18 [RSMD0603_1/10W-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I93 R19 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 UNNAMED_1_MAX9601_I1_IN_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+
+RSMD0603_1/10W I93 R20 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_2 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 UNNAMED_1_MAX9601_I1_IN_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+
+RSMD0603_1/10W I93 R21 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 UNNAMED_1_MAX9601_I1_IN_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+
+RSMD0603_1/10W I93 R22 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_1_PCOAXSMD_I168_A_4 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ 2 UNNAMED_1_MAX9601_I1_IN_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+
+RSMD0805_125MW I148 R23 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0805_125MW I148 R24 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0805_125MW I148 R25 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0805_125MW I148 R26 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I73 R27 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I71_HYS_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I73 R28 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I71_HYS_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I73 R29 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I71_HYS_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I73 R30 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I71_HYS_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0805_125MW I147 R31 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0805_125MW I147 R32 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0805_125MW I147 R33 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0805_125MW I147 R34 [RSMD0805_125MW-100,1%]
+ 2 UNNAMED_1_MAX9601_I1_IN_1_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I146 R35 [RSMD0603_1/10W-3.3,1%]
+ 2 UNNAMED_1_CAPCERSMDCL2_I81_A_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_CAPCERSMDCL2_I81_A
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I81 R36 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I1_HYS_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I81 R37 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I1_HYS_2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I81 R38 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I1_HYS_3 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I81 R39 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_MAX9601_I1_HYS_4 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I23 R40 [RSMD0603_1/10W-10K,1%]
+ 2 VTHRESH<0> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<0>
+ 1 UNNAMED_1_OPA4277_I22_MIN A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I29@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I23 R41 [RSMD0603_1/10W-10K,1%]
+ 2 VTHRESH<3> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<3>
+ 1 UNNAMED_1_OPA4277_I22_MIN_1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I30@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I113 R42 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER*<3> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<3>
+
+RSMD0603_1/10W I113 R43 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER*<2> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<2>
+
+RSMD0603_1/10W I113 R44 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER*<1> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<1>
+
+RSMD0603_1/10W I113 R45 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER*<0> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<0>
+
+RSMD0603_1/10W I24 R46 [RSMD0603_1/10W-10K,1%]
+ 1 VREF A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ 2 UNNAMED_1_OPA4277_I22_MIN B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I29@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I24 R47 [RSMD0603_1/10W-10K,1%]
+ 1 VREF A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ 2 UNNAMED_1_OPA4277_I22_MIN_1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I30@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+
+RSMD0603_1/10W I111 R48 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER<3> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<3>
+
+RSMD0603_1/10W I111 R49 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER<2> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<2>
+
+RSMD0603_1/10W I111 R50 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER<1> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<1>
+
+RSMD0603_1/10W I111 R51 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER<0> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<0>
+
+RSMD0603_1/10W I152 R52 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD<3> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<3>
+
+RSMD0603_1/10W I152 R53 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD<2> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<2>
+
+RSMD0603_1/10W I152 R54 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD<1> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<1>
+
+RSMD0603_1/10W I152 R55 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD<0> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<0>
+
+RSMD0603_1/10W I153 R56 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD*<2> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<2>
+
+RSMD0603_1/10W I153 R57 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD*<1> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<1>
+
+RSMD0603_1/10W I153 R58 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD*<0> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<0>
+
+RSMD0603_1/10W I153 R59 [RSMD0603_1/10W-75,1%]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 BEAM_TRIGGER_CFD*<3> B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<3>
+
+RSMD0603_ I15 R60 [RSMD0603_-00,]
+ 1 UNNAMED_1_24AA025E48_I8_A0 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A0
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I12 R61 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_24AA025E48_I8_A0 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A0
+ 1 P3V3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+
+RSMD0603_ I16 R62 [RSMD0603_-00,]
+ 1 UNNAMED_1_24AA025E48_I8_A1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A1
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I13 R63 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_24AA025E48_I8_A1 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A1
+ 1 P3V3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+
+RSMD0603_ I17 R64 [RSMD0603_-00,]
+ 1 UNNAMED_1_24AA025E48_I8_A2 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A2
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I14 R65 [RSMD0603_1/10W-XX,1%]
+ 2 UNNAMED_1_24AA025E48_I8_A2 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A2
+ 1 P3V3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+
+RSMD0603_1/10W I10 R66 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_4_CAPCERSMDCL2_I9_B A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I9_B
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I11 R67 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_4_CAPCERSMDCL2_I8_B A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I8_B
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I38 R68 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_4_CAPCERSMDCL2_I41_B A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I41_B
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I39 R69 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_4_CAPCERSMDCL2_I42_B A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I42_B
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I18 R70 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_4_CAPCERSMDCL2_I19_B A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I19_B
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I21 R71 [RSMD0603_1/10W-51,1%]
+ 1 UNNAMED_4_CAPCERSMDCL2_I22_B A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I22_B
+ 2 GND_SIGNAL B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I74 R72 [RSMD0603_1/10W-6.19K,1%]
+ 2 UNNAMED_1_LTM8047_I70_ADJ_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_LTM8047_I70_ADJ
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+RSMD0603_1/10W I85 R73 [RSMD0603_1/10W-6.19K,1%]
+ 2 UNNAMED_1_LTM8047_I82_ADJ_6 B<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_LTM8047_I82_ADJ
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+LT1175_SOT_223 I40 REG1 []
+ 4 M5V7_6 V_IN1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):M5V7
+ 2 M5V7_6 V_IN0 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):M5V7
+ 1 M5V V_OUT @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ 3 GND_SIGNAL GND @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+LTM8047_BGA I70 RG1 [LTM8047EY#PBF]
+ C5 VM2<0>_6 VOUT-<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ C4 VM2<0>_6 VOUT-<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ C3 VM2<0>_6 VOUT-<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ C2 VM2<0>_6 VOUT-<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ C1 VM2<0>_6 VOUT-<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ B5 VM2<0>_6 VOUT-<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ B4 VM2<0>_6 VOUT-<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ B3 VM2<0>_6 VOUT-<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ B2 VM2<0>_6 VOUT-<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ B1 VM2<0>_6 VOUT-<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ A5 VM2<0>_6 VOUT-<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ A4 VM2<0>_6 VOUT-<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ A3 VM2<0>_6 VOUT-<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ A2 VM2<0>_6 VOUT-<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ A1 VM2<0>_6 VOUT-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ G2 VIN_FILTERED_6 VIN<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ G1 VIN_FILTERED_6 VIN<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ H2 VIN_FILTERED_6 VIN<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ H1 VIN_FILTERED_6 VIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ F3 VIN_FILTERED_6 RUN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ H5 VIN_FILTERED_6 BIAS @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ G7 UNNAMED_1_LTM8047_I70_ADJ_6 ADJ @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_LTM8047_I70_ADJ
+ H6 NC SS NC
+ C7 GND_SIGNAL VOUT<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C6 GND_SIGNAL VOUT<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ B7 GND_SIGNAL VOUT<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ B6 GND_SIGNAL VOUT<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ A7 GND_SIGNAL VOUT<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ A6 GND_SIGNAL VOUT<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H7 GND_SIGNAL GND<15> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H4 GND_SIGNAL GND<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G6 GND_SIGNAL GND<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G5 GND_SIGNAL GND<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G4 GND_SIGNAL GND<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F7 GND_SIGNAL GND<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F6 GND_SIGNAL GND<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F5 GND_SIGNAL GND<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F4 GND_SIGNAL GND<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E7 GND_SIGNAL GND<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E6 GND_SIGNAL GND<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E5 GND_SIGNAL GND<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E4 GND_SIGNAL GND<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E3 GND_SIGNAL GND<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E2 GND_SIGNAL GND<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E1 GND_SIGNAL GND<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+LTM8047_BGA I82 RG2 [LTM8047EY#PBF]
+ C7 VP1<0>_6 VOUT<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ C6 VP1<0>_6 VOUT<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ B7 VP1<0>_6 VOUT<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ B6 VP1<0>_6 VOUT<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ A7 VP1<0>_6 VOUT<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ A6 VP1<0>_6 VOUT<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ G2 VIN_FILTERED_6 VIN<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ G1 VIN_FILTERED_6 VIN<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ H2 VIN_FILTERED_6 VIN<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ H1 VIN_FILTERED_6 VIN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ F3 VIN_FILTERED_6 RUN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ H5 VIN_FILTERED_6 BIAS @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ G7 UNNAMED_1_LTM8047_I82_ADJ_6 ADJ @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_LTM8047_I82_ADJ
+ H6 NC SS NC
+ C5 GND_SIGNAL VOUT-<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C4 GND_SIGNAL VOUT-<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C3 GND_SIGNAL VOUT-<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C2 GND_SIGNAL VOUT-<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C1 GND_SIGNAL VOUT-<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ B5 GND_SIGNAL VOUT-<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ B4 GND_SIGNAL VOUT-<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ B3 GND_SIGNAL VOUT-<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ B2 GND_SIGNAL VOUT-<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ B1 GND_SIGNAL VOUT-<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ A5 GND_SIGNAL VOUT-<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ A4 GND_SIGNAL VOUT-<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ A3 GND_SIGNAL VOUT-<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ A2 GND_SIGNAL VOUT-<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ A1 GND_SIGNAL VOUT-<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H7 GND_SIGNAL GND<15> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ H4 GND_SIGNAL GND<14> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G6 GND_SIGNAL GND<13> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G5 GND_SIGNAL GND<12> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ G4 GND_SIGNAL GND<11> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F7 GND_SIGNAL GND<10> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F6 GND_SIGNAL GND<9> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F5 GND_SIGNAL GND<8> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ F4 GND_SIGNAL GND<7> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E7 GND_SIGNAL GND<6> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E6 GND_SIGNAL GND<5> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E5 GND_SIGNAL GND<4> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E4 GND_SIGNAL GND<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E3 GND_SIGNAL GND<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E2 GND_SIGNAL GND<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ E1 GND_SIGNAL GND<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TRANS MOSFET_GSD I26 T1 [TRANS MOSFET_GSD-FDV301N,SOT23]
+ 2 UNNAMED_4_CON19P_I2_A S @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CON19P_I2_A
+ 1 UNNAMED_4_74LVC1G07_I28_Y G @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I28_Y
+ 3 P3V3 D @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+
+TRANS MOSFET_GSD I45 T2 [TRANS MOSFET_GSD-FDV301N,SOT23]
+ 2 UNNAMED_4_CON19P_I3_A S @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CON19P_I3_A
+ 1 UNNAMED_4_74LVC1G07_I40_Y G @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I40_Y
+ 3 P3V3 D @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+
+TP_HOLE I75 TP1 [TP_HOLE-0.8MM]
+ 1 CLK1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1
+
+TP_HOLE I76 TP2 [TP_HOLE-0.8MM]
+ 1 CLK1* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1*
+
+TP_HOLE I70 TP3 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I67 TP4 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I73 TP5 [TP_HOLE-0.8MM]
+ 1 BUSY1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1
+
+TP_HOLE I74 TP6 [TP_HOLE-0.8MM]
+ 1 BUSY1* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1*
+
+TP_HOLE I71 TP7 [TP_HOLE-0.8MM]
+ 1 CTRIG1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1
+
+TP_HOLE I72 TP8 [TP_HOLE-0.8MM]
+ 1 CTRIG1* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1*
+
+TP_HOLE I68 TP9 [TP_HOLE-0.8MM]
+ 1 CONT1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1
+
+TP_HOLE I69 TP10 [TP_HOLE-0.8MM]
+ 1 CONT1* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1*
+
+TP_HOLE I65 TP11 [TP_HOLE-0.8MM]
+ 1 SPARE1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1
+
+TP_HOLE I66 TP12 [TP_HOLE-0.8MM]
+ 1 SPARE1* A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1*
+
+TP_HOLE I68 TP13 [TP_HOLE-0.8MM]
+ 1 VREF A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+
+TP_HOLE I162 TP14 [TP_HOLE-0.8MM]
+ 1 UNNAMED_1_CAPCERSMDCL2_I78_B_1 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+TP_HOLE I162 TP15 [TP_HOLE-0.8MM]
+ 1 UNNAMED_1_CAPCERSMDCL2_I78_B_2 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+TP_HOLE I162 TP16 [TP_HOLE-0.8MM]
+ 1 UNNAMED_1_CAPCERSMDCL2_I78_B_3 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+TP_HOLE I162 TP17 [TP_HOLE-0.8MM]
+ 1 UNNAMED_1_CAPCERSMDCL2_I78_B_4 A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+
+TP_HOLE I159 TP18 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER<3> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<3>
+
+TP_HOLE I159 TP19 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER<2> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<2>
+
+TP_HOLE I159 TP20 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER<1> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<1>
+
+TP_HOLE I159 TP21 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER<0> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<0>
+
+TP_HOLE I69 TP22 [TP_HOLE-0.8MM]
+ 1 UNNAMED_1_AD5665R_I63_VOUTA A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTA
+
+TP_HOLE I161 TP23 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I161 TP24 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I161 TP25 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I161 TP26 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I160 TP27 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER*<3> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<3>
+
+TP_HOLE I164 TP28 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD*<3> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<3>
+
+TP_HOLE I163 TP29 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD<3> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<3>
+
+TP_HOLE I164 TP30 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD*<2> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<2>
+
+TP_HOLE I163 TP31 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD<2> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<2>
+
+TP_HOLE I164 TP32 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD*<1> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<1>
+
+TP_HOLE I163 TP33 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD<1> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<1>
+
+TP_HOLE I164 TP34 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD*<0> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<0>
+
+TP_HOLE I163 TP35 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER_CFD<0> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<0>
+
+TP_HOLE I160 TP36 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER*<2> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<2>
+
+TP_HOLE I160 TP37 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER*<1> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<1>
+
+TP_HOLE I160 TP38 [TP_HOLE-0.8MM]
+ 1 BEAM_TRIGGER*<0> A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<0>
+
+TP_HOLE I165 TP39 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I165 TP40 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I165 TP41 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+TP_HOLE I165 TP42 [TP_HOLE-0.8MM]
+ 1 GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+PRTR5V0U8S_TSSOP I48 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 10 SPARE2* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2*
+
+PRTR5V0U8S_TSSOP I7 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 9 SPARE2 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2
+
+PRTR5V0U8S_TSSOP I45 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 7 BUSY2* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2*
+
+PRTR5V0U8S_TSSOP I44 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 6 BUSY2 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2
+
+PRTR5V0U8S_TSSOP I50 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 5 CONT2* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2*
+
+PRTR5V0U8S_TSSOP I43 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 4 CONT2 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2
+
+PRTR5V0U8S_TSSOP I47 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 2 CLK2 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2
+
+PRTR5V0U8S_TSSOP I46 U1 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 1 CLK2* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2*
+
+PRTR5V0U8S_TSSOP I48 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 10 SPARE1* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1*
+
+PRTR5V0U8S_TSSOP I7 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 9 SPARE1 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1
+
+PRTR5V0U8S_TSSOP I45 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 7 BUSY1* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1*
+
+PRTR5V0U8S_TSSOP I44 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 6 BUSY1 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1
+
+PRTR5V0U8S_TSSOP I50 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 5 CONT1* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1*
+
+PRTR5V0U8S_TSSOP I43 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 4 CONT1 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1
+
+PRTR5V0U8S_TSSOP I47 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 2 CLK1 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1
+
+PRTR5V0U8S_TSSOP I46 U2 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 1 CLK1* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1*
+
+PRTR5V0U8S_TSSOP I50 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 10 DUT_CLK0* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0*
+
+PRTR5V0U8S_TSSOP I43 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 9 DUT_CLK0 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0
+
+PRTR5V0U8S_TSSOP I46 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 7 CONT0 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0
+
+PRTR5V0U8S_TSSOP I45 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 6 CONT0* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0*
+
+PRTR5V0U8S_TSSOP I44 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 5 BUSY0* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0*
+
+PRTR5V0U8S_TSSOP I47 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 4 BUSY0 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0
+
+PRTR5V0U8S_TSSOP I48 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 2 TRIG0* IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0*
+
+PRTR5V0U8S_TSSOP I7 U3 [PRTR5V0U8S_TSSOP-NXP-GND=GND_SA]
+ 1 TRIG0 IN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0
+
+LP5951_SOT23-5 I70 U4 [LP5951_SOT23-5-1.3V,TEXAS INSTA]
+ 5 VREF VOUT @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ 1 P3V3 VIN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 3 P3V3 ON/OFF @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ 2 GND_SIGNAL GND @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+LT1129CST-5_SOT223 I50 VR1 [LT1129CST-5_SOT223-LINEAR]
+ 1 P5V7_6 VIN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):P5V7
+ 3 P5V VOUT @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ 4 GND_SIGNAL TAB @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ 2 GND_SIGNAL GND @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+ZENER_SOD123-CA I51 Z1 [ZENER_SOD123-CA-BZT52C2V7]
+ C P2V5 K<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ A GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+ZENER_SOD123-CA I51 Z2 [ZENER_SOD123-CA-BZT52C2V7]
+ C P2V5 K<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ A GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+ZENER_SOD123-CA I51 Z3 [ZENER_SOD123-CA-BZT52C2V7]
+ C P2V5 K<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ A GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+
+ZENER_SOD123-CA I98 Z4 [ZENER_SOD123-CA-BZT52C2V7]
+ C P2V5 K<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ A GND_SIGNAL A<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+END OF PART CROSS REFERENCE
+
+SIGNAL CROSS REFERENCE (forward interface)
+
+BEAM_TRIGGER*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<0>
+ IC7 19 Q*<0> MAX9601_TSSOP I71
+ J4 G37 G<37> CON160P_40CDGH I1
+ R45 2 B<0> RSMD0603_1/10W I113
+ TP38 1 A<0> TP_HOLE I160
+
+BEAM_TRIGGER*<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<1>
+ IC6 19 Q*<0> MAX9601_TSSOP I71
+ J4 G34 G<34> CON160P_40CDGH I1
+ R44 2 B<0> RSMD0603_1/10W I113
+ TP37 1 A<0> TP_HOLE I160
+
+BEAM_TRIGGER*<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<2>
+ IC5 19 Q*<0> MAX9601_TSSOP I71
+ J4 G31 G<31> CON160P_40CDGH I1
+ R43 2 B<0> RSMD0603_1/10W I113
+ TP36 1 A<0> TP_HOLE I160
+
+BEAM_TRIGGER*<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER*<3>
+ IC4 19 Q*<0> MAX9601_TSSOP I71
+ J4 G28 G<28> CON160P_40CDGH I1
+ R42 2 B<0> RSMD0603_1/10W I113
+ TP27 1 A<0> TP_HOLE I160
+
+BEAM_TRIGGER<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<0>
+ IC7 20 Q<0> MAX9601_TSSOP I71
+ J4 G36 G<36> CON160P_40CDGH I1
+ R51 2 B<0> RSMD0603_1/10W I111
+ TP21 1 A<0> TP_HOLE I159
+
+BEAM_TRIGGER<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<1>
+ IC6 20 Q<0> MAX9601_TSSOP I71
+ J4 G33 G<33> CON160P_40CDGH I1
+ R50 2 B<0> RSMD0603_1/10W I111
+ TP20 1 A<0> TP_HOLE I159
+
+BEAM_TRIGGER<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<2>
+ IC5 20 Q<0> MAX9601_TSSOP I71
+ J4 G30 G<30> CON160P_40CDGH I1
+ R49 2 B<0> RSMD0603_1/10W I111
+ TP19 1 A<0> TP_HOLE I159
+
+BEAM_TRIGGER<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER<3>
+ IC4 20 Q<0> MAX9601_TSSOP I71
+ J4 G27 G<27> CON160P_40CDGH I1
+ R48 2 B<0> RSMD0603_1/10W I111
+ TP18 1 A<0> TP_HOLE I159
+
+BEAM_TRIGGER_CFD*<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<0>
+ IC7 2 Q*<0> MAX9601_TSSOP I1
+ J4 H38 H<38> CON160P_40CDGH I1
+ R58 2 B<0> RSMD0603_1/10W I153
+ TP34 1 A<0> TP_HOLE I164
+
+BEAM_TRIGGER_CFD*<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<1>
+ IC6 2 Q*<0> MAX9601_TSSOP I1
+ J4 H35 H<35> CON160P_40CDGH I1
+ R57 2 B<0> RSMD0603_1/10W I153
+ TP32 1 A<0> TP_HOLE I164
+
+BEAM_TRIGGER_CFD*<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<2>
+ IC5 2 Q*<0> MAX9601_TSSOP I1
+ J4 H32 H<32> CON160P_40CDGH I1
+ R56 2 B<0> RSMD0603_1/10W I153
+ TP30 1 A<0> TP_HOLE I164
+
+BEAM_TRIGGER_CFD*<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD*<3>
+ IC4 2 Q*<0> MAX9601_TSSOP I1
+ J4 H29 H<29> CON160P_40CDGH I1
+ R59 2 B<0> RSMD0603_1/10W I153
+ TP28 1 A<0> TP_HOLE I164
+
+BEAM_TRIGGER_CFD<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<0>
+ IC7 1 Q<0> MAX9601_TSSOP I1
+ J4 H37 H<37> CON160P_40CDGH I1
+ R55 2 B<0> RSMD0603_1/10W I152
+ TP35 1 A<0> TP_HOLE I163
+
+BEAM_TRIGGER_CFD<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<1>
+ IC6 1 Q<0> MAX9601_TSSOP I1
+ J4 H34 H<34> CON160P_40CDGH I1
+ R54 2 B<0> RSMD0603_1/10W I152
+ TP33 1 A<0> TP_HOLE I163
+
+BEAM_TRIGGER_CFD<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<2>
+ IC5 1 Q<0> MAX9601_TSSOP I1
+ J4 H31 H<31> CON160P_40CDGH I1
+ R53 2 B<0> RSMD0603_1/10W I152
+ TP31 1 A<0> TP_HOLE I163
+
+BEAM_TRIGGER_CFD<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BEAM_TRIGGER_CFD<3>
+ IC4 1 Q<0> MAX9601_TSSOP I1
+ J4 H28 H<28> CON160P_40CDGH I1
+ R52 2 B<0> RSMD0603_1/10W I152
+ TP29 1 A<0> TP_HOLE I163
+
+BUSY0 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0
+ J3 6 A<5> CON8P I78
+ J4 H22 H<22> CON160P_40CDGH I1
+ U3 4 IN PRTR5V0U8S_TSSOP I47
+
+BUSY0* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY0*
+ J3 3 A<2> CON8P I78
+ J4 H23 H<23> CON160P_40CDGH I1
+ U3 5 IN PRTR5V0U8S_TSSOP I44
+
+BUSY1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1
+ J1 7 A<6> CON19P I2
+ J4 C18 C<18> CON160P_40CDGH I2
+ TP5 1 A<0> TP_HOLE I73
+ U2 6 IN PRTR5V0U8S_TSSOP I44
+
+BUSY1* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY1*
+ J1 9 A<8> CON19P I2
+ J4 C19 C<19> CON160P_40CDGH I2
+ TP6 1 A<0> TP_HOLE I74
+ U2 7 IN PRTR5V0U8S_TSSOP I45
+
+BUSY2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2
+ J2 7 A<6> CON19P I3
+ J4 G15 G<15> CON160P_40CDGH I1
+ U1 6 IN PRTR5V0U8S_TSSOP I44
+
+BUSY2* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):BUSY2*
+ J2 9 A<8> CON19P I3
+ J4 G16 G<16> CON160P_40CDGH I1
+ U1 7 IN PRTR5V0U8S_TSSOP I45
+
+CLK1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1
+ J1 3 A<2> CON19P I2
+ J4 C26 C<26> CON160P_40CDGH I2
+ TP1 1 A<0> TP_HOLE I75
+ U2 2 IN PRTR5V0U8S_TSSOP I47
+
+CLK1* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK1*
+ J1 1 A<0> CON19P I2
+ J4 C27 C<27> CON160P_40CDGH I2
+ TP2 1 A<0> TP_HOLE I76
+ U2 1 IN PRTR5V0U8S_TSSOP I46
+
+CLK2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2
+ J2 3 A<2> CON19P I3
+ J4 H7 H<7> CON160P_40CDGH I1
+ U1 2 IN PRTR5V0U8S_TSSOP I47
+
+CLK2* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK2*
+ J2 1 A<0> CON19P I3
+ J4 H8 H<8> CON160P_40CDGH I1
+ U1 1 IN PRTR5V0U8S_TSSOP I46
+
+CONT0 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0
+ J3 5 A<4> CON8P I78
+ J4 G24 G<24> CON160P_40CDGH I1
+ U3 7 IN PRTR5V0U8S_TSSOP I46
+
+CONT0* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT0*
+ J3 4 A<3> CON8P I78
+ J4 G25 G<25> CON160P_40CDGH I1
+ U3 6 IN PRTR5V0U8S_TSSOP I45
+
+CONT1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1
+ J1 4 A<3> CON19P I2
+ J4 C22 C<22> CON160P_40CDGH I2
+ TP9 1 A<0> TP_HOLE I68
+ U2 4 IN PRTR5V0U8S_TSSOP I43
+
+CONT1* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT1*
+ J1 6 A<5> CON19P I2
+ J4 C23 C<23> CON160P_40CDGH I2
+ TP10 1 A<0> TP_HOLE I69
+ U2 5 IN PRTR5V0U8S_TSSOP I50
+
+CONT2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2
+ J2 4 A<3> CON19P I3
+ J4 H13 H<13> CON160P_40CDGH I1
+ U1 4 IN PRTR5V0U8S_TSSOP I43
+
+CONT2* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CONT2*
+ J2 6 A<5> CON19P I3
+ J4 H14 H<14> CON160P_40CDGH I1
+ U1 5 IN PRTR5V0U8S_TSSOP I50
+
+CTRIG1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1
+ D2 3 I/O2<0> USBLC6-2_SOT23 I33
+ J1 15 A<14> CON19P I2
+ TP7 1 A<0> TP_HOLE I71
+
+CTRIG1* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG1*
+ D2 1 I/O1<0> USBLC6-2_SOT23 I33
+ J1 16 A<15> CON19P I2
+ TP8 1 A<0> TP_HOLE I72
+
+CTRIG2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG2
+ D1 3 I/O2<0> USBLC6-2_SOT23 I49
+ J2 15 A<14> CON19P I3
+
+CTRIG2* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CTRIG2*
+ D1 1 I/O1<0> USBLC6-2_SOT23 I49
+ J2 16 A<15> CON19P I3
+
+DUT_CLK0 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0
+ J3 2 A<1> CON8P I78
+ J4 H25 H<25> CON160P_40CDGH I1
+ U3 9 IN PRTR5V0U8S_TSSOP I43
+
+DUT_CLK0* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):DUT_CLK0*
+ J3 1 A<0> CON8P I78
+ J4 H26 H<26> CON160P_40CDGH I1
+ U3 10 IN PRTR5V0U8S_TSSOP I50
+
+FMC_LA*<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK_IO_2
+ J4 G3 G<3> CON160P_40CDGH I1
+ PL1 8 A<7> CON16P I93
+
+FMC_LA<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):CLK_IO_1
+ J4 G2 G<2> CON160P_40CDGH I1
+ PL1 4 A<3> CON16P I93
+
+FMC_LA<29> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GPIO_CLK
+ J4 G6 G<6> CON160P_40CDGH I1
+ PL1 6 A<5> CON16P I93
+
+FRAME @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRAME
+ C52 1 A<0> CAPCERSMDCL2_0603 I19
+ C53 1 A<0> CAPCERSMDCL2_0603 I22
+
+FRONT_PANEL_CLK @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRONT_PANEL_CLK
+ D3 6 I/O1<1> USBLC6-2_SOT23 I92
+ J4 H4 H<4> CON160P_40CDGH I1
+
+FRONT_PANEL_CLK* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):FRONT_PANEL_CLK*
+ D3 4 I/O2<1> USBLC6-2_SOT23 I92
+ J4 H5 H<5> CON160P_40CDGH I1
+
+GND_HDMI1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_HDMI1
+ C48 1 A<0> CAPCERSMDCL2_0603 I9
+ C49 1 A<0> CAPCERSMDCL2_0603 I8
+
+GND_HDMI2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_HDMI2
+ C46 1 A<0> CAPCERSMDCL2_0603 I42
+ C47 1 A<0> CAPCERSMDCL2_0603 I41
+
+GND_SIGNAL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):GND_SIGNAL
+ C1 1 A<0> CAPCERSMDCL2_0603 I90
+ C6 1 A<0> CAPCERSMDCL2_0603 I51
+ C7 1 A<0> CAPCERSMDCL2_0805 I58
+ C8 1 A<0> CAPCERSMDCL2_0805 I56
+ C9 1 A<0> CAPCERSMDCL2_1210 I79
+ C10 1 A<0> CAPCERSMDCL2_0805 I52
+ C11 1 A<0> CAPCERSMDCL2_0603 I78
+ C12 1 A<0> CAPCERSMDCL2_0603 I78
+ C13 1 A<0> CAPCERSMDCL2_0603 I78
+ C14 1 A<0> CAPCERSMDCL2_0603 I78
+ C15 1 A<0> CAPCERSMDCL2_0603 I44
+ C16 1 A<0> CAPCERSMDCL2_0603 I44
+ C17 1 A<0> CAPCERSMDCL2_0603 I44
+ C18 1 A<0> CAPCERSMDCL2_0603 I44
+ C19 1 A<0> CAPCERSMDCL2_0603 I151
+ C20 1 A<0> CAPCERSMDCL2_0603 I151
+ C21 1 A<0> CAPCERSMDCL2_0603 I151
+ C22 1 A<0> CAPCERSMDCL2_0603 I151
+ C23 1 A<0> CAPCERSMDCL2_0805 I54
+ C24 1 A<0> CAPCERSMDCL2_0603 I150
+ C25 1 A<0> CAPCERSMDCL2_0603 I150
+ C26 1 A<0> CAPCERSMDCL2_0603 I150
+ C27 1 A<0> CAPCERSMDCL2_0603 I150
+ C29 1 A<0> CAPCERSMDCL2_0603 I73
+ C30 1 A<0> CAPCERSMDCL2_0603 I39
+ C31 1 A<0> CAPCERSMDCL2_0603 I39
+ C32 1 A<0> CAPCERSMDCL2_0603 I39
+ C33 1 A<0> CAPCERSMDCL2_0603 I39
+ C34 1 A<0> CAPCERSMDCL2_1210 I72
+ C35 1 A<0> CAPCERSMDCL2_1210 I88
+ C36 1 A<0> CAPCERSMDCL2_0603 I47
+ C37 1 A<0> CAPCERSMDCL2_0603 I47
+ C38 1 A<0> CAPCERSMDCL2_0603 I47
+ C39 1 A<0> CAPCERSMDCL2_0603 I47
+ C40 1 A<0> CAPCERSMDCL2_0603 I50
+ C41 1 A<0> CAPCERSMDCL2_1210 I142
+ C42 1 A<0> CAPCERSMDCL2_0603 I53
+ C43 1 A<0> CAPCERSMDCL2_1210 I83
+ C44 1 A<0> CAPCERSMDCL2_1210 I144
+ C45 1 A<0> CAPCERSMDCL2_1210 I89
+ C50 2 B<0> CAPCERSMDCL2_0603 I60
+ C51 2 B<0> CAPCERSMDCL2_0603 I56
+ C54 1 A<0> CAPCERSMDCL2_0603 I9
+ C55 1 A<0> CAPCERSMDCL2_0603 I9
+ C56 1 A<0> CAPCERSMDCL2_0603 I9
+ C57 1 A<0> CAPCERSMDCL2_0603 I40
+ C58 1 A<0> CAPCERSMDCL2_0603 I41
+ C59 1 A<0> CAPCERSMDCL2_0603 I40
+ C60 1 A<0> CAPCERSMDCL2_0603 I41
+ C61 1 A<0> CAPCERSMDCL2_0603 I40
+ C62 1 A<0> CAPCERSMDCL2_0603 I41
+ C63 1 A<0> CAPCERSMDCL2_0603 I40
+ C64 1 A<0> CAPCERSMDCL2_0603 I41
+ C65 2 B<0> CAPCERSMDCL2_0603 I52
+ C66 1 A<0> CAPCERSMDCL2_0603 I43
+ C67 1 A<0> CAPCERSMDCL2_0603 I43
+ C68 1 A<0> CAPCERSMDCL2_0603 I43
+ C69 1 A<0> CAPCERSMDCL2_0603 I43
+ C70 2 B<0> CAPCERSMDCL2_0603 I11
+ C71 1 A<0> CAPCERSMDCL2_0603 I66
+ D1 2 GND USBLC6-2_SOT23 I49
+ D2 2 GND USBLC6-2_SOT23 I33
+ D3 2 GND USBLC6-2_SOT23 I92
+ IC4 4 LE<0> MAX9601_TSSOP I1
+ IC4 17 LE<0> MAX9601_TSSOP I71
+ IC5 4 LE<0> MAX9601_TSSOP I1
+ IC5 17 LE<0> MAX9601_TSSOP I71
+ IC6 4 LE<0> MAX9601_TSSOP I1
+ IC6 17 LE<0> MAX9601_TSSOP I71
+ IC7 4 LE<0> MAX9601_TSSOP I1
+ IC7 17 LE<0> MAX9601_TSSOP I71
+ IC8 1 LDAC* AD5665R_TSSOP I63
+ IC8 2 ADDR1 AD5665R_TSSOP I63
+ IC8 8 ADDR2 AD5665R_TSSOP I63
+ IC9 4 VSS 24AA025E48_SOIC I8
+ J1 2 A<1> CON19P I2
+ J1 5 A<4> CON19P I2
+ J1 8 A<7> CON19P I2
+ J1 11 A<10> CON19P I2
+ J1 17 A<16> CON19P I2
+ J2 2 A<1> CON19P I3
+ J2 5 A<4> CON19P I3
+ J2 8 A<7> CON19P I3
+ J2 11 A<10> CON19P I3
+ J2 17 A<16> CON19P I3
+ J4 C1 C<1> CON160P_40CDGH I2
+ J4 C4 C<4> CON160P_40CDGH I2
+ J4 C5 C<5> CON160P_40CDGH I2
+ J4 C8 C<8> CON160P_40CDGH I2
+ J4 C9 C<9> CON160P_40CDGH I2
+ J4 C12 C<12> CON160P_40CDGH I2
+ J4 C13 C<13> CON160P_40CDGH I2
+ J4 C16 C<16> CON160P_40CDGH I2
+ J4 C17 C<17> CON160P_40CDGH I2
+ J4 C20 C<20> CON160P_40CDGH I2
+ J4 C21 C<21> CON160P_40CDGH I2
+ J4 C24 C<24> CON160P_40CDGH I2
+ J4 C25 C<25> CON160P_40CDGH I2
+ J4 C28 C<28> CON160P_40CDGH I2
+ J4 C29 C<29> CON160P_40CDGH I2
+ J4 C32 C<32> CON160P_40CDGH I2
+ J4 C33 C<33> CON160P_40CDGH I2
+ J4 C36 C<36> CON160P_40CDGH I2
+ J4 C38 C<38> CON160P_40CDGH I2
+ J4 C40 C<40> CON160P_40CDGH I2
+ J4 D2 D<2> CON160P_40CDGH I2
+ J4 D3 D<3> CON160P_40CDGH I2
+ J4 D6 D<6> CON160P_40CDGH I2
+ J4 D7 D<7> CON160P_40CDGH I2
+ J4 D10 D<10> CON160P_40CDGH I2
+ J4 D13 D<13> CON160P_40CDGH I2
+ J4 D16 D<16> CON160P_40CDGH I2
+ J4 D19 D<19> CON160P_40CDGH I2
+ J4 D22 D<22> CON160P_40CDGH I2
+ J4 D25 D<25> CON160P_40CDGH I2
+ J4 D28 D<28> CON160P_40CDGH I2
+ J4 D37 D<37> CON160P_40CDGH I2
+ J4 D39 D<39> CON160P_40CDGH I2
+ J4 G1 G<1> CON160P_40CDGH I1
+ J4 G4 G<4> CON160P_40CDGH I1
+ J4 G5 G<5> CON160P_40CDGH I1
+ J4 G8 G<8> CON160P_40CDGH I1
+ J4 G11 G<11> CON160P_40CDGH I1
+ J4 G14 G<14> CON160P_40CDGH I1
+ J4 G17 G<17> CON160P_40CDGH I1
+ J4 G20 G<20> CON160P_40CDGH I1
+ J4 G23 G<23> CON160P_40CDGH I1
+ J4 G26 G<26> CON160P_40CDGH I1
+ J4 G29 G<29> CON160P_40CDGH I1
+ J4 G32 G<32> CON160P_40CDGH I1
+ J4 G35 G<35> CON160P_40CDGH I1
+ J4 G38 G<38> CON160P_40CDGH I1
+ J4 G40 G<40> CON160P_40CDGH I1
+ J4 H3 H<3> CON160P_40CDGH I1
+ J4 H6 H<6> CON160P_40CDGH I1
+ J4 H9 H<9> CON160P_40CDGH I1
+ J4 H12 H<12> CON160P_40CDGH I1
+ J4 H15 H<15> CON160P_40CDGH I1
+ J4 H18 H<18> CON160P_40CDGH I1
+ J4 H21 H<21> CON160P_40CDGH I1
+ J4 H24 H<24> CON160P_40CDGH I1
+ J4 H27 H<27> CON160P_40CDGH I1
+ J4 H30 H<30> CON160P_40CDGH I1
+ J4 H33 H<33> CON160P_40CDGH I1
+ J4 H36 H<36> CON160P_40CDGH I1
+ J4 H39 H<39> CON160P_40CDGH I1
+ PL1 3 A<2> CON16P I93
+ PL1 5 A<4> CON16P I93
+ PL1 7 A<6> CON16P I93
+ PL1 9 A<8> CON16P I93
+ PL1 11 A<10> CON16P I93
+ PL1 13 A<12> CON16P I93
+ R15 1 A<0> RSMD0603_1/10W I92
+ R16 1 A<0> RSMD0603_1/10W I92
+ R17 1 A<0> RSMD0603_1/10W I92
+ R18 1 A<0> RSMD0603_1/10W I92
+ R23 1 A<0> RSMD0805_125MW I148
+ R24 1 A<0> RSMD0805_125MW I148
+ R25 1 A<0> RSMD0805_125MW I148
+ R26 1 A<0> RSMD0805_125MW I148
+ R27 1 A<0> RSMD0603_1/10W I73
+ R28 1 A<0> RSMD0603_1/10W I73
+ R29 1 A<0> RSMD0603_1/10W I73
+ R30 1 A<0> RSMD0603_1/10W I73
+ R31 1 A<0> RSMD0805_125MW I147
+ R32 1 A<0> RSMD0805_125MW I147
+ R33 1 A<0> RSMD0805_125MW I147
+ R34 1 A<0> RSMD0805_125MW I147
+ R35 1 A<0> RSMD0603_1/10W I146
+ R36 1 A<0> RSMD0603_1/10W I81
+ R37 1 A<0> RSMD0603_1/10W I81
+ R38 1 A<0> RSMD0603_1/10W I81
+ R39 1 A<0> RSMD0603_1/10W I81
+ R42 1 A<0> RSMD0603_1/10W I113
+ R43 1 A<0> RSMD0603_1/10W I113
+ R44 1 A<0> RSMD0603_1/10W I113
+ R45 1 A<0> RSMD0603_1/10W I113
+ R48 1 A<0> RSMD0603_1/10W I111
+ R49 1 A<0> RSMD0603_1/10W I111
+ R50 1 A<0> RSMD0603_1/10W I111
+ R51 1 A<0> RSMD0603_1/10W I111
+ R52 1 A<0> RSMD0603_1/10W I152
+ R53 1 A<0> RSMD0603_1/10W I152
+ R54 1 A<0> RSMD0603_1/10W I152
+ R55 1 A<0> RSMD0603_1/10W I152
+ R56 1 A<0> RSMD0603_1/10W I153
+ R57 1 A<0> RSMD0603_1/10W I153
+ R58 1 A<0> RSMD0603_1/10W I153
+ R59 1 A<0> RSMD0603_1/10W I153
+ R60 2 B<0> RSMD0603_ I15
+ R62 2 B<0> RSMD0603_ I16
+ R64 2 B<0> RSMD0603_ I17
+ R66 2 B<0> RSMD0603_1/10W I10
+ R67 2 B<0> RSMD0603_1/10W I11
+ R68 2 B<0> RSMD0603_1/10W I38
+ R69 2 B<0> RSMD0603_1/10W I39
+ R70 2 B<0> RSMD0603_1/10W I18
+ R71 2 B<0> RSMD0603_1/10W I21
+ R72 1 A<0> RSMD0603_1/10W I74
+ R73 1 A<0> RSMD0603_1/10W I85
+ REG1 3 GND LT1175_SOT_223 I40
+ RG1 A6 VOUT<0> LTM8047_BGA I70
+ RG1 A7 VOUT<1> LTM8047_BGA I70
+ RG1 B6 VOUT<2> LTM8047_BGA I70
+ RG1 B7 VOUT<3> LTM8047_BGA I70
+ RG1 C6 VOUT<4> LTM8047_BGA I70
+ RG1 C7 VOUT<5> LTM8047_BGA I70
+ RG1 E1 GND<0> LTM8047_BGA I70
+ RG1 E2 GND<1> LTM8047_BGA I70
+ RG1 E3 GND<2> LTM8047_BGA I70
+ RG1 E4 GND<3> LTM8047_BGA I70
+ RG1 E5 GND<4> LTM8047_BGA I70
+ RG1 E6 GND<5> LTM8047_BGA I70
+ RG1 E7 GND<6> LTM8047_BGA I70
+ RG1 F4 GND<7> LTM8047_BGA I70
+ RG1 F5 GND<8> LTM8047_BGA I70
+ RG1 F6 GND<9> LTM8047_BGA I70
+ RG1 F7 GND<10> LTM8047_BGA I70
+ RG1 G4 GND<11> LTM8047_BGA I70
+ RG1 G5 GND<12> LTM8047_BGA I70
+ RG1 G6 GND<13> LTM8047_BGA I70
+ RG1 H4 GND<14> LTM8047_BGA I70
+ RG1 H7 GND<15> LTM8047_BGA I70
+ RG2 A1 VOUT-<0> LTM8047_BGA I82
+ RG2 A2 VOUT-<1> LTM8047_BGA I82
+ RG2 A3 VOUT-<2> LTM8047_BGA I82
+ RG2 A4 VOUT-<3> LTM8047_BGA I82
+ RG2 A5 VOUT-<4> LTM8047_BGA I82
+ RG2 B1 VOUT-<5> LTM8047_BGA I82
+ RG2 B2 VOUT-<6> LTM8047_BGA I82
+ RG2 B3 VOUT-<7> LTM8047_BGA I82
+ RG2 B4 VOUT-<8> LTM8047_BGA I82
+ RG2 B5 VOUT-<9> LTM8047_BGA I82
+ RG2 C1 VOUT-<10> LTM8047_BGA I82
+ RG2 C2 VOUT-<11> LTM8047_BGA I82
+ RG2 C3 VOUT-<12> LTM8047_BGA I82
+ RG2 C4 VOUT-<13> LTM8047_BGA I82
+ RG2 C5 VOUT-<14> LTM8047_BGA I82
+ RG2 E1 GND<0> LTM8047_BGA I82
+ RG2 E2 GND<1> LTM8047_BGA I82
+ RG2 E3 GND<2> LTM8047_BGA I82
+ RG2 E4 GND<3> LTM8047_BGA I82
+ RG2 E5 GND<4> LTM8047_BGA I82
+ RG2 E6 GND<5> LTM8047_BGA I82
+ RG2 E7 GND<6> LTM8047_BGA I82
+ RG2 F4 GND<7> LTM8047_BGA I82
+ RG2 F5 GND<8> LTM8047_BGA I82
+ RG2 F6 GND<9> LTM8047_BGA I82
+ RG2 F7 GND<10> LTM8047_BGA I82
+ RG2 G4 GND<11> LTM8047_BGA I82
+ RG2 G5 GND<12> LTM8047_BGA I82
+ RG2 G6 GND<13> LTM8047_BGA I82
+ RG2 H4 GND<14> LTM8047_BGA I82
+ RG2 H7 GND<15> LTM8047_BGA I82
+ TP3 1 A<0> TP_HOLE I70
+ TP4 1 A<0> TP_HOLE I67
+ TP23 1 A<0> TP_HOLE I161
+ TP24 1 A<0> TP_HOLE I161
+ TP25 1 A<0> TP_HOLE I161
+ TP26 1 A<0> TP_HOLE I161
+ TP39 1 A<0> TP_HOLE I165
+ TP40 1 A<0> TP_HOLE I165
+ TP41 1 A<0> TP_HOLE I165
+ TP42 1 A<0> TP_HOLE I165
+ U4 2 GND LP5951_SOT23-5 I70
+ VR1 2 GND LT1129CST-5_SOT223 I50
+ VR1 4 TAB LT1129CST-5_SOT223 I50
+ Z1 A A<0> ZENER_SOD123-CA I51
+ Z2 A A<0> ZENER_SOD123-CA I51
+ Z3 A A<0> ZENER_SOD123-CA I51
+ Z4 A A<0> ZENER_SOD123-CA I98
+
+HDMI_POWER_ENABLE1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):HDMI_POWER_ENABLE1
+ IC2 2 A 74LVC1G07_SC70 I28
+ J4 H10 H<10> CON160P_40CDGH I1
+
+HDMI_POWER_ENABLE2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):HDMI_POWER_ENABLE2
+ IC1 2 A 74LVC1G07_SC70 I40
+ J4 H20 H<20> CON160P_40CDGH I1
+
+IN<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<0>
+ D7 3 AC DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ IC7 12 IN-<0> MAX9601_TSSOP I71
+ PX5 1 A PCOAX I51
+ R14 2 B<0> RSMD0805_125MW I94
+
+IN<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<1>
+ D6 3 AC DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ IC6 12 IN-<0> MAX9601_TSSOP I71
+ PX4 1 A PCOAX I52
+ R13 2 B<0> RSMD0805_125MW I94
+
+IN<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<2>
+ D5 3 AC DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ IC5 12 IN-<0> MAX9601_TSSOP I71
+ PX3 1 A PCOAX I53
+ R12 2 B<0> RSMD0805_125MW I94
+
+IN<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):IN<3>
+ D4 3 AC DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ IC4 12 IN-<0> MAX9601_TSSOP I71
+ PX2 1 A PCOAX I54
+ R11 2 B<0> RSMD0805_125MW I94
+
+M5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):M5V
+ C2 1 A<0> CAPCERSMDCL2_0603 I123
+ C3 1 A<0> CAPCERSMDCL2_0603 I123
+ C4 1 A<0> CAPCERSMDCL2_0603 I123
+ C5 1 A<0> CAPCERSMDCL2_0603 I123
+ C7 2 B<0> CAPCERSMDCL2_0805 I58
+ C15 2 B<0> CAPCERSMDCL2_0603 I44
+ C16 2 B<0> CAPCERSMDCL2_0603 I44
+ C17 2 B<0> CAPCERSMDCL2_0603 I44
+ C18 2 B<0> CAPCERSMDCL2_0603 I44
+ C65 1 A<0> CAPCERSMDCL2_0603 I52
+ C66 2 B<0> CAPCERSMDCL2_0603 I43
+ C67 2 B<0> CAPCERSMDCL2_0603 I43
+ C68 2 B<0> CAPCERSMDCL2_0603 I43
+ C69 2 B<0> CAPCERSMDCL2_0603 I43
+ D4 1 A DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ D5 1 A DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ D6 1 A DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ D7 1 A DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ IC3 11 V- OPA4277_SOIC I22
+ IC4 6 VEE<0> MAX9601_TSSOP I1
+ IC4 15 VEE<1> MAX9601_TSSOP I1
+ IC5 6 VEE<0> MAX9601_TSSOP I1
+ IC5 15 VEE<1> MAX9601_TSSOP I1
+ IC6 6 VEE<0> MAX9601_TSSOP I1
+ IC6 15 VEE<1> MAX9601_TSSOP I1
+ IC7 6 VEE<0> MAX9601_TSSOP I1
+ IC7 15 VEE<1> MAX9601_TSSOP I1
+ PL1 16 A<15> CON16P I93
+ REG1 1 V_OUT LT1175_SOT_223 I40
+
+M5V7_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):M5V7
+ C23 2 B<0> CAPCERSMDCL2_0805 I54
+ L2 2 B FERRITE_SMD I44
+ REG1 2 V_IN0 LT1175_SOT_223 I40
+ REG1 4 V_IN1 LT1175_SOT_223 I40
+
+NC NC
+ J4 H1 H<1> CON160P_40CDGH I1
+ J4 D34 D<34> CON160P_40CDGH I2
+ J4 D5 D<5> CON160P_40CDGH I2
+ J4 D4 D<4> CON160P_40CDGH I2
+ J4 D35 D<35> CON160P_40CDGH I2
+ J4 C34 C<34> CON160P_40CDGH I2
+ J4 D30 D<30> CON160P_40CDGH I2
+ J4 D33 D<33> CON160P_40CDGH I2
+ J4 D31 D<31> CON160P_40CDGH I2
+ J4 D29 D<29> CON160P_40CDGH I2
+ J4 D1 D<1> CON160P_40CDGH I2
+ J4 H2 H<2> CON160P_40CDGH I1
+ J4 D14 D<14> CON160P_40CDGH I2
+ J4 C10 C<10> CON160P_40CDGH I2
+ J4 D11 D<11> CON160P_40CDGH I2
+ J4 D26 D<26> CON160P_40CDGH I2
+ J4 D23 D<23> CON160P_40CDGH I2
+ J4 D8 D<8> CON160P_40CDGH I2
+ J4 D20 D<20> CON160P_40CDGH I2
+ J4 H19 H<19> CON160P_40CDGH I1
+ J4 D17 D<17> CON160P_40CDGH I2
+ J4 C14 C<14> CON160P_40CDGH I2
+ J4 D15 D<15> CON160P_40CDGH I2
+ J4 C11 C<11> CON160P_40CDGH I2
+ J4 D12 D<12> CON160P_40CDGH I2
+ J4 H11 H<11> CON160P_40CDGH I1
+ J4 D27 D<27> CON160P_40CDGH I2
+ J4 D24 D<24> CON160P_40CDGH I2
+ J4 D9 D<9> CON160P_40CDGH I2
+ J4 D21 D<21> CON160P_40CDGH I2
+ J4 D18 D<18> CON160P_40CDGH I2
+ J4 C15 C<15> CON160P_40CDGH I2
+ J4 G7 G<7> CON160P_40CDGH I1
+ J4 C7 C<7> CON160P_40CDGH I2
+ J4 C6 C<6> CON160P_40CDGH I2
+ J4 C3 C<3> CON160P_40CDGH I2
+ J4 C2 C<2> CON160P_40CDGH I2
+ RG2 H6 SS LTM8047_BGA I82
+ RG1 H6 SS LTM8047_BGA I70
+ PL1 10 A<9> CON16P I93
+ J2 19 A<18> CON19P I3
+ J2 18 A<17> CON19P I3
+ J2 13 A<12> CON19P I3
+ J1 19 A<18> CON19P I2
+ J1 18 A<17> CON19P I2
+ J1 13 A<12> CON19P I2
+
+P12V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P12V
+ C9 2 B<0> CAPCERSMDCL2_1210 I79
+ J4 C35 C<35> CON160P_40CDGH I2
+ J4 C37 C<37> CON160P_40CDGH I2
+ L1 1 A FERRITE_SMD I66
+
+P2V5 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P2V5
+ C1 2 B<0> CAPCERSMDCL2_0603 I90
+ C19 2 B<0> CAPCERSMDCL2_0603 I151
+ C20 2 B<0> CAPCERSMDCL2_0603 I151
+ C21 2 B<0> CAPCERSMDCL2_0603 I151
+ C22 2 B<0> CAPCERSMDCL2_0603 I151
+ C24 2 B<0> CAPCERSMDCL2_0603 I150
+ C25 2 B<0> CAPCERSMDCL2_0603 I150
+ C26 2 B<0> CAPCERSMDCL2_0603 I150
+ C27 2 B<0> CAPCERSMDCL2_0603 I150
+ C36 2 B<0> CAPCERSMDCL2_0603 I47
+ C37 2 B<0> CAPCERSMDCL2_0603 I47
+ C38 2 B<0> CAPCERSMDCL2_0603 I47
+ C39 2 B<0> CAPCERSMDCL2_0603 I47
+ C50 1 A<0> CAPCERSMDCL2_0603 I60
+ C51 1 A<0> CAPCERSMDCL2_0603 I56
+ C54 2 B<0> CAPCERSMDCL2_0603 I9
+ C55 2 B<0> CAPCERSMDCL2_0603 I9
+ C56 2 B<0> CAPCERSMDCL2_0603 I9
+ D1 5 VBUS USBLC6-2_SOT23 I49
+ D2 5 VBUS USBLC6-2_SOT23 I33
+ D3 5 VBUS USBLC6-2_SOT23 I92
+ IC4 3 VCCO_<0> MAX9601_TSSOP I1
+ IC4 5 LE*<0> MAX9601_TSSOP I1
+ IC4 16 LE*<0> MAX9601_TSSOP I71
+ IC4 18 VCCO_<1> MAX9601_TSSOP I1
+ IC5 3 VCCO_<0> MAX9601_TSSOP I1
+ IC5 5 LE*<0> MAX9601_TSSOP I1
+ IC5 16 LE*<0> MAX9601_TSSOP I71
+ IC5 18 VCCO_<1> MAX9601_TSSOP I1
+ IC6 3 VCCO_<0> MAX9601_TSSOP I1
+ IC6 5 LE*<0> MAX9601_TSSOP I1
+ IC6 16 LE*<0> MAX9601_TSSOP I71
+ IC6 18 VCCO_<1> MAX9601_TSSOP I1
+ IC7 3 VCCO_<0> MAX9601_TSSOP I1
+ IC7 5 LE*<0> MAX9601_TSSOP I1
+ IC7 16 LE*<0> MAX9601_TSSOP I71
+ IC7 18 VCCO_<1> MAX9601_TSSOP I1
+ J4 G39 G<39> CON160P_40CDGH I1
+ J4 H40 H<40> CON160P_40CDGH I1
+ Z1 C K<0> ZENER_SOD123-CA I51
+ Z2 C K<0> ZENER_SOD123-CA I51
+ Z3 C K<0> ZENER_SOD123-CA I51
+ Z4 C K<0> ZENER_SOD123-CA I98
+
+P3V3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P3V3
+ C29 2 B<0> CAPCERSMDCL2_0603 I73
+ C40 2 B<0> CAPCERSMDCL2_0603 I50
+ C42 2 B<0> CAPCERSMDCL2_0603 I53
+ C70 1 A<0> CAPCERSMDCL2_0603 I11
+ IC8 6 POR AD5665R_TSSOP I63
+ IC8 9 CLR* AD5665R_TSSOP I63
+ IC9 8 VCC 24AA025E48_SOIC I8
+ J4 C39 C<39> CON160P_40CDGH I2
+ J4 D32 D<32> CON160P_40CDGH I2
+ J4 D36 D<36> CON160P_40CDGH I2
+ J4 D38 D<38> CON160P_40CDGH I2
+ J4 D40 D<40> CON160P_40CDGH I2
+ PL1 1 A<0> CON16P I93
+ PL1 2 A<1> CON16P I93
+ R61 1 A<0> RSMD0603_1/10W I12
+ R63 1 A<0> RSMD0603_1/10W I13
+ R65 1 A<0> RSMD0603_1/10W I14
+ T1 3 D TRANS MOSFET_GSD I26
+ T2 3 D TRANS MOSFET_GSD I45
+ U4 1 VIN LP5951_SOT23-5 I70
+ U4 3 ON/OFF LP5951_SOT23-5 I70
+
+P5V @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):P5V
+ C2 2 B<0> CAPCERSMDCL2_0603 I123
+ C3 2 B<0> CAPCERSMDCL2_0603 I123
+ C4 2 B<0> CAPCERSMDCL2_0603 I123
+ C5 2 B<0> CAPCERSMDCL2_0603 I123
+ C6 2 B<0> CAPCERSMDCL2_0603 I51
+ C8 2 B<0> CAPCERSMDCL2_0805 I56
+ C30 2 B<0> CAPCERSMDCL2_0603 I39
+ C31 2 B<0> CAPCERSMDCL2_0603 I39
+ C32 2 B<0> CAPCERSMDCL2_0603 I39
+ C33 2 B<0> CAPCERSMDCL2_0603 I39
+ C57 2 B<0> CAPCERSMDCL2_0603 I40
+ C58 2 B<0> CAPCERSMDCL2_0603 I41
+ C59 2 B<0> CAPCERSMDCL2_0603 I40
+ C60 2 B<0> CAPCERSMDCL2_0603 I41
+ C61 2 B<0> CAPCERSMDCL2_0603 I40
+ C62 2 B<0> CAPCERSMDCL2_0603 I41
+ C63 2 B<0> CAPCERSMDCL2_0603 I40
+ C64 2 B<0> CAPCERSMDCL2_0603 I41
+ D4 2 C DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ D5 2 C DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ D6 2 C DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ D7 2 C DIODE_DUAL_SERIES_A1-C2-AC3 I120
+ IC3 4 V+ OPA4277_SOIC I22
+ IC4 7 VCC<0> MAX9601_TSSOP I1
+ IC4 14 VCC<1> MAX9601_TSSOP I1
+ IC5 7 VCC<0> MAX9601_TSSOP I1
+ IC5 14 VCC<1> MAX9601_TSSOP I1
+ IC6 7 VCC<0> MAX9601_TSSOP I1
+ IC6 14 VCC<1> MAX9601_TSSOP I1
+ IC7 7 VCC<0> MAX9601_TSSOP I1
+ IC7 14 VCC<1> MAX9601_TSSOP I1
+ PL1 15 A<14> CON16P I93
+ R1 2 B<0> RSMD0603_1/10W I29
+ R2 2 B<0> RSMD0603_1/10W I44
+ VR1 3 VOUT LT1129CST-5_SOT223 I50
+
+P5V7_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):P5V7
+ C10 2 B<0> CAPCERSMDCL2_0805 I52
+ L3 2 B FERRITE_SMD I42
+ VR1 1 VIN LT1129CST-5_SOT223 I50
+
+SCL @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SCL
+ IC8 14 SCL AD5665R_TSSOP I63
+ IC9 6 SCL 24AA025E48_SOIC I8
+ J4 C30 C<30> CON160P_40CDGH I2
+ PL1 14 A<13> CON16P I93
+
+SDA @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SDA
+ IC8 13 SDA AD5665R_TSSOP I63
+ IC9 5 SDA 24AA025E48_SOIC I8
+ J4 C31 C<31> CON160P_40CDGH I2
+ PL1 12 A<11> CON16P I93
+
+SPARE1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1
+ J1 10 A<9> CON19P I2
+ J4 G12 G<12> CON160P_40CDGH I1
+ TP11 1 A<0> TP_HOLE I65
+ U2 9 IN PRTR5V0U8S_TSSOP I7
+
+SPARE1* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE1*
+ J1 12 A<11> CON19P I2
+ J4 G13 G<13> CON160P_40CDGH I1
+ TP12 1 A<0> TP_HOLE I66
+ U2 10 IN PRTR5V0U8S_TSSOP I48
+
+SPARE2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2
+ J2 10 A<9> CON19P I3
+ J4 H16 H<16> CON160P_40CDGH I1
+ U1 9 IN PRTR5V0U8S_TSSOP I7
+
+SPARE2* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):SPARE2*
+ J2 12 A<11> CON19P I3
+ J4 H17 H<17> CON160P_40CDGH I1
+ U1 10 IN PRTR5V0U8S_TSSOP I48
+
+TRIG0 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0
+ J3 8 A<7> CON8P I78
+ J4 G21 G<21> CON160P_40CDGH I1
+ U3 1 IN PRTR5V0U8S_TSSOP I7
+
+TRIG0* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG0*
+ J3 7 A<6> CON8P I78
+ J4 G22 G<22> CON160P_40CDGH I1
+ U3 2 IN PRTR5V0U8S_TSSOP I48
+
+TRIG1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG1
+ D2 4 I/O2<1> USBLC6-2_SOT23 I33
+ J4 G9 G<9> CON160P_40CDGH I1
+
+TRIG1* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG1*
+ D2 6 I/O1<1> USBLC6-2_SOT23 I33
+ J4 G10 G<10> CON160P_40CDGH I1
+
+TRIG2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG2
+ D1 4 I/O2<1> USBLC6-2_SOT23 I49
+ J4 G18 G<18> CON160P_40CDGH I1
+
+TRIG2* @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):TRIG2*
+ D1 6 I/O1<1> USBLC6-2_SOT23 I49
+ J4 G19 G<19> CON160P_40CDGH I1
+
+UNNAMED_1_24AA025E48_I8_A0 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A0
+ IC9 1 A0 24AA025E48_SOIC I8
+ R60 1 A<0> RSMD0603_ I15
+ R61 2 B<0> RSMD0603_1/10W I12
+
+UNNAMED_1_24AA025E48_I8_A1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A1
+ IC9 2 A1 24AA025E48_SOIC I8
+ R62 1 A<0> RSMD0603_ I16
+ R63 2 B<0> RSMD0603_1/10W I13
+
+UNNAMED_1_24AA025E48_I8_A2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_24AA025E48_I8_A2
+ IC9 3 A2 24AA025E48_SOIC I8
+ R64 1 A<0> RSMD0603_ I17
+ R65 2 B<0> RSMD0603_1/10W I14
+
+UNNAMED_1_AD5665R_I63_VOUTA @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTA
+ IC3 3 PIN<0> OPA4277_SOIC I22
+ IC8 4 VOUTA AD5665R_TSSOP I63
+ TP22 1 A<0> TP_HOLE I69
+
+UNNAMED_1_AD5665R_I63_VOUTB @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTB
+ IC3 12 PIN<0> OPA4277_SOIC I22
+ IC8 11 VOUTB AD5665R_TSSOP I63
+
+UNNAMED_1_AD5665R_I63_VOUTC @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTC
+ IC3 10 PIN<0> OPA4277_SOIC I22
+ IC8 5 VOUTC AD5665R_TSSOP I63
+
+UNNAMED_1_AD5665R_I63_VOUTD @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):UNNAMED_1_AD5665R_I63_VOUTD
+ IC3 5 PIN<0> OPA4277_SOIC I22
+ IC8 10 VOUTD AD5665R_TSSOP I63
+
+UNNAMED_1_CAPCERSMDCL2_I78_B_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ C11 2 B<0> CAPCERSMDCL2_0603 I78
+ IC4 11 IN+<0> MAX9601_TSSOP I71
+ R7 2 B<0> RSMD0603_1/10W I79
+ TP14 1 A<0> TP_HOLE I162
+
+UNNAMED_1_CAPCERSMDCL2_I78_B_2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ C12 2 B<0> CAPCERSMDCL2_0603 I78
+ IC5 11 IN+<0> MAX9601_TSSOP I71
+ R8 2 B<0> RSMD0603_1/10W I79
+ TP15 1 A<0> TP_HOLE I162
+
+UNNAMED_1_CAPCERSMDCL2_I78_B_3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ C13 2 B<0> CAPCERSMDCL2_0603 I78
+ IC6 11 IN+<0> MAX9601_TSSOP I71
+ R9 2 B<0> RSMD0603_1/10W I79
+ TP16 1 A<0> TP_HOLE I162
+
+UNNAMED_1_CAPCERSMDCL2_I78_B_4 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_CAPCERSMDCL2_I78_B
+ C14 2 B<0> CAPCERSMDCL2_0603 I78
+ IC7 11 IN+<0> MAX9601_TSSOP I71
+ R10 2 B<0> RSMD0603_1/10W I79
+ TP17 1 A<0> TP_HOLE I162
+
+UNNAMED_1_CAPCERSMDCL2_I81_A_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_CAPCERSMDCL2_I81_A
+ C28 1 A<0> CAPCERSMDCL2_1210 I81
+ R35 2 B<0> RSMD0603_1/10W I146
+
+UNNAMED_1_LTM8047_I70_ADJ_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_LTM8047_I70_ADJ
+ R72 2 B<0> RSMD0603_1/10W I74
+ RG1 G7 ADJ LTM8047_BGA I70
+
+UNNAMED_1_LTM8047_I82_ADJ_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):UNNAMED_1_LTM8047_I82_ADJ
+ R73 2 B<0> RSMD0603_1/10W I85
+ RG2 G7 ADJ LTM8047_BGA I82
+
+UNNAMED_1_MAX9601_I1_HYS_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ IC4 8 HYS<0> MAX9601_TSSOP I1
+ R36 2 B<0> RSMD0603_1/10W I81
+
+UNNAMED_1_MAX9601_I1_HYS_2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ IC5 8 HYS<0> MAX9601_TSSOP I1
+ R37 2 B<0> RSMD0603_1/10W I81
+
+UNNAMED_1_MAX9601_I1_HYS_3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ IC6 8 HYS<0> MAX9601_TSSOP I1
+ R38 2 B<0> RSMD0603_1/10W I81
+
+UNNAMED_1_MAX9601_I1_HYS_4 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_HYS
+ IC7 8 HYS<0> MAX9601_TSSOP I1
+ R39 2 B<0> RSMD0603_1/10W I81
+
+UNNAMED_1_MAX9601_I1_IN_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ IC4 10 IN+<0> MAX9601_TSSOP I1
+ R15 2 B<0> RSMD0603_1/10W I92
+ R19 2 B<0> RSMD0603_1/10W I93
+
+UNNAMED_1_MAX9601_I1_IN_1_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ IC4 9 IN-<0> MAX9601_TSSOP I1
+ PX10 1 A PCOAXSMD I169
+ R23 2 B<0> RSMD0805_125MW I148
+ R31 2 B<0> RSMD0805_125MW I147
+
+UNNAMED_1_MAX9601_I1_IN_1_2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ IC5 9 IN-<0> MAX9601_TSSOP I1
+ PX11 1 A PCOAXSMD I169
+ R24 2 B<0> RSMD0805_125MW I148
+ R32 2 B<0> RSMD0805_125MW I147
+
+UNNAMED_1_MAX9601_I1_IN_1_3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ IC6 9 IN-<0> MAX9601_TSSOP I1
+ PX12 1 A PCOAXSMD I169
+ R25 2 B<0> RSMD0805_125MW I148
+ R33 2 B<0> RSMD0805_125MW I147
+
+UNNAMED_1_MAX9601_I1_IN_1_4 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN_1
+ IC7 9 IN-<0> MAX9601_TSSOP I1
+ PX13 1 A PCOAXSMD I169
+ R26 2 B<0> RSMD0805_125MW I148
+ R34 2 B<0> RSMD0805_125MW I147
+
+UNNAMED_1_MAX9601_I1_IN_2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ IC5 10 IN+<0> MAX9601_TSSOP I1
+ R16 2 B<0> RSMD0603_1/10W I92
+ R20 2 B<0> RSMD0603_1/10W I93
+
+UNNAMED_1_MAX9601_I1_IN_3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ IC6 10 IN+<0> MAX9601_TSSOP I1
+ R17 2 B<0> RSMD0603_1/10W I92
+ R21 2 B<0> RSMD0603_1/10W I93
+
+UNNAMED_1_MAX9601_I1_IN_4 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I1_IN
+ IC7 10 IN+<0> MAX9601_TSSOP I1
+ R18 2 B<0> RSMD0603_1/10W I92
+ R22 2 B<0> RSMD0603_1/10W I93
+
+UNNAMED_1_MAX9601_I71_HYS_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ IC4 13 HYS<0> MAX9601_TSSOP I71
+ R27 2 B<0> RSMD0603_1/10W I73
+
+UNNAMED_1_MAX9601_I71_HYS_2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ IC5 13 HYS<0> MAX9601_TSSOP I71
+ R28 2 B<0> RSMD0603_1/10W I73
+
+UNNAMED_1_MAX9601_I71_HYS_3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ IC6 13 HYS<0> MAX9601_TSSOP I71
+ R29 2 B<0> RSMD0603_1/10W I73
+
+UNNAMED_1_MAX9601_I71_HYS_4 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_MAX9601_I71_HYS
+ IC7 13 HYS<0> MAX9601_TSSOP I71
+ R30 2 B<0> RSMD0603_1/10W I73
+
+UNNAMED_1_OPA4277_I22_MIN @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I29@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ IC3 2 MIN<0> OPA4277_SOIC I22
+ R40 1 A<0> RSMD0603_1/10W I23
+ R46 2 B<0> RSMD0603_1/10W I24
+
+UNNAMED_1_OPA4277_I22_MIN_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I30@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ IC3 6 MIN<0> OPA4277_SOIC I22
+ R41 1 A<0> RSMD0603_1/10W I23
+ R47 2 B<0> RSMD0603_1/10W I24
+
+UNNAMED_1_OPA4277_I22_MIN_2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I31@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ IC3 9 MIN<0> OPA4277_SOIC I22
+ R4 2 B<0> RSMD0603_1/10W I24
+ R5 1 A<0> RSMD0603_1/10W I23
+
+UNNAMED_1_OPA4277_I22_MIN_3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):PAGE1_I32@FMC_TLU_V1_LIB.PC023A_VTHRESH_BUFFER(SCH_1):UNNAMED_1_OPA4277_I22_MIN
+ IC3 13 MIN<0> OPA4277_SOIC I22
+ R3 2 B<0> RSMD0603_1/10W I24
+ R6 1 A<0> RSMD0603_1/10W I23
+
+UNNAMED_1_PCOAXSMD_I168_A_1 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I35@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ PX6 1 A PCOAXSMD I168
+ R11 1 A<0> RSMD0805_125MW I94
+ R19 1 A<0> RSMD0603_1/10W I93
+
+UNNAMED_1_PCOAXSMD_I168_A_2 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I36@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ PX7 1 A PCOAXSMD I168
+ R12 1 A<0> RSMD0805_125MW I94
+ R20 1 A<0> RSMD0603_1/10W I93
+
+UNNAMED_1_PCOAXSMD_I168_A_3 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I37@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ PX8 1 A PCOAXSMD I168
+ R13 1 A<0> RSMD0805_125MW I94
+ R21 1 A<0> RSMD0603_1/10W I93
+
+UNNAMED_1_PCOAXSMD_I168_A_4 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I38@FMC_TLU_V1_LIB.FMC_TLU_CFD(SCH_1):UNNAMED_1_PCOAXSMD_I168_A
+ PX9 1 A PCOAXSMD I168
+ R14 1 A<0> RSMD0805_125MW I94
+ R22 1 A<0> RSMD0603_1/10W I93
+
+UNNAMED_1_PLEMO2CI_I7_A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_PLEMO2CI_I7_A
+ D3 1 I/O1<0> USBLC6-2_SOT23 I92
+ PX1 1 A PLEMO2CI I7
+
+UNNAMED_1_PLEMO2CI_I7_B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_1_PLEMO2CI_I7_B
+ D3 3 I/O2<0> USBLC6-2_SOT23 I92
+ PX1 2 B PLEMO2CI I7
+
+UNNAMED_4_74LVC1G07_I28_Y @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I28_Y
+ IC2 4 Y 74LVC1G07_SC70 I28
+ R1 1 A<0> RSMD0603_1/10W I29
+ T1 1 G TRANS MOSFET_GSD I26
+
+UNNAMED_4_74LVC1G07_I40_Y @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_74LVC1G07_I40_Y
+ IC1 4 Y 74LVC1G07_SC70 I40
+ R2 1 A<0> RSMD0603_1/10W I44
+ T2 1 G TRANS MOSFET_GSD I45
+
+UNNAMED_4_CAPCERSMDCL2_I19_B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I19_B
+ C52 2 B<0> CAPCERSMDCL2_0603 I19
+ R70 1 A<0> RSMD0603_1/10W I18
+
+UNNAMED_4_CAPCERSMDCL2_I22_B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I22_B
+ C53 2 B<0> CAPCERSMDCL2_0603 I22
+ R71 1 A<0> RSMD0603_1/10W I21
+
+UNNAMED_4_CAPCERSMDCL2_I41_B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I41_B
+ C47 2 B<0> CAPCERSMDCL2_0603 I41
+ R68 1 A<0> RSMD0603_1/10W I38
+
+UNNAMED_4_CAPCERSMDCL2_I42_B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I42_B
+ C46 2 B<0> CAPCERSMDCL2_0603 I42
+ R69 1 A<0> RSMD0603_1/10W I39
+
+UNNAMED_4_CAPCERSMDCL2_I8_B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I8_B
+ C49 2 B<0> CAPCERSMDCL2_0603 I8
+ R67 1 A<0> RSMD0603_1/10W I11
+
+UNNAMED_4_CAPCERSMDCL2_I9_B @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CAPCERSMDCL2_I9_B
+ C48 2 B<0> CAPCERSMDCL2_0603 I9
+ R66 1 A<0> RSMD0603_1/10W I10
+
+UNNAMED_4_CON19P_I2_A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CON19P_I2_A
+ J1 14 A<13> CON19P I2
+ T1 2 S TRANS MOSFET_GSD I26
+
+UNNAMED_4_CON19P_I3_A @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):UNNAMED_4_CON19P_I3_A
+ J2 14 A<13> CON19P I3
+ T2 2 S TRANS MOSFET_GSD I45
+
+VIN_FILTERED_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VIN_FILTERED
+ C28 2 B<0> CAPCERSMDCL2_1210 I81
+ C34 2 B<0> CAPCERSMDCL2_1210 I72
+ C41 2 B<0> CAPCERSMDCL2_1210 I142
+ C43 2 B<0> CAPCERSMDCL2_1210 I83
+ C44 2 B<0> CAPCERSMDCL2_1210 I144
+ L1 2 B FERRITE_SMD I66
+ RG1 F3 RUN LTM8047_BGA I70
+ RG1 G1 VIN<2> LTM8047_BGA I70
+ RG1 G2 VIN<3> LTM8047_BGA I70
+ RG1 H1 VIN<0> LTM8047_BGA I70
+ RG1 H2 VIN<1> LTM8047_BGA I70
+ RG1 H5 BIAS LTM8047_BGA I70
+ RG2 F3 RUN LTM8047_BGA I82
+ RG2 G1 VIN<2> LTM8047_BGA I82
+ RG2 G2 VIN<3> LTM8047_BGA I82
+ RG2 H1 VIN<0> LTM8047_BGA I82
+ RG2 H2 VIN<1> LTM8047_BGA I82
+ RG2 H5 BIAS LTM8047_BGA I82
+
+VM2<0>_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VM2<0>
+ C35 2 B<0> CAPCERSMDCL2_1210 I88
+ L2 1 A FERRITE_SMD I44
+ RG1 A1 VOUT-<0> LTM8047_BGA I70
+ RG1 A2 VOUT-<1> LTM8047_BGA I70
+ RG1 A3 VOUT-<2> LTM8047_BGA I70
+ RG1 A4 VOUT-<3> LTM8047_BGA I70
+ RG1 A5 VOUT-<4> LTM8047_BGA I70
+ RG1 B1 VOUT-<5> LTM8047_BGA I70
+ RG1 B2 VOUT-<6> LTM8047_BGA I70
+ RG1 B3 VOUT-<7> LTM8047_BGA I70
+ RG1 B4 VOUT-<8> LTM8047_BGA I70
+ RG1 B5 VOUT-<9> LTM8047_BGA I70
+ RG1 C1 VOUT-<10> LTM8047_BGA I70
+ RG1 C2 VOUT-<11> LTM8047_BGA I70
+ RG1 C3 VOUT-<12> LTM8047_BGA I70
+ RG1 C4 VOUT-<13> LTM8047_BGA I70
+ RG1 C5 VOUT-<14> LTM8047_BGA I70
+
+VP1<0>_6 @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I55@FMC_TLU_V1_LIB.FMC_TLU_VSUPPLY5V(SCH_1):VP1<0>
+ C45 2 B<0> CAPCERSMDCL2_1210 I89
+ L3 1 A FERRITE_SMD I42
+ RG2 A6 VOUT<0> LTM8047_BGA I82
+ RG2 A7 VOUT<1> LTM8047_BGA I82
+ RG2 B6 VOUT<2> LTM8047_BGA I82
+ RG2 B7 VOUT<3> LTM8047_BGA I82
+ RG2 C6 VOUT<4> LTM8047_BGA I82
+ RG2 C7 VOUT<5> LTM8047_BGA I82
+
+VREF @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):PAGE2_I5@FMC_TLU_V1_LIB.PC023A_DAC_VTHRESH(SCH_1):VREF
+ C71 2 B<0> CAPCERSMDCL2_0603 I66
+ IC8 7 VREFIN/VREFOUT AD5665R_TSSOP I63
+ R3 1 A<0> RSMD0603_1/10W I24
+ R4 1 A<0> RSMD0603_1/10W I24
+ R46 1 A<0> RSMD0603_1/10W I24
+ R47 1 A<0> RSMD0603_1/10W I24
+ TP13 1 A<0> TP_HOLE I68
+ U4 5 VOUT LP5951_SOT23-5 I70
+
+VTHRESH<0> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<0>
+ IC3 1 OUT<0> OPA4277_SOIC I22
+ R10 1 A<0> RSMD0603_1/10W I79
+ R40 2 B<0> RSMD0603_1/10W I23
+
+VTHRESH<1> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<1>
+ IC3 14 OUT<0> OPA4277_SOIC I22
+ R6 2 B<0> RSMD0603_1/10W I23
+ R9 1 A<0> RSMD0603_1/10W I79
+
+VTHRESH<2> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<2>
+ IC3 8 OUT<0> OPA4277_SOIC I22
+ R5 2 B<0> RSMD0603_1/10W I23
+ R8 1 A<0> RSMD0603_1/10W I79
+
+VTHRESH<3> @FMC_TLU_V1_LIB.FMC_TLU_TOPLEVEL_B(SCH_1):VTHRESH<3>
+ IC3 7 OUT<0> OPA4277_SOIC I22
+ R7 1 A<0> RSMD0603_1/10W I79
+ R41 2 B<0> RSMD0603_1/10W I23
+END OF SIGNAL CROSS REFERENCE
+**** Part Type 'DIODE_DUAL_SERIES_A1-C2-AC3' ('HBAT-540C') ****
+**** Part Type 'LP5951_SOT23-5' ('LP5951_SOT23-5-1.3V,TEXAS INSTA') ****
+**** Part Type 'LT1129CST-5_SOT223' ('LT1129CST-5_SOT223-LINEAR') ****
+**** Part Type 'LT1175_SOT_223' ('LT1175_SOT_223') ****
+**** Part Type 'LTM8047_BGA' ('LTM8047EY#PBF') ****
+**** Part Type 'MAX9601_TSSOP' ('MAX9601_TSSOP') ****
+**** Part Type 'OPA4277_SOIC' ('OPA4277UA') ****
+**** Part Type 'PCOAX' ('PCOAX-PLEMO00C-GND=GND_SIGNAL') ****
+**** Part Type 'PCOAXSMD' ('PCOAXSMD-UFL_R_SMT-GND=GND_SIGA') ****
+**** Part Type 'PLEMO2CI' ('PLEMO2CI-PLEMO2-00B-GND=GND_SIA') ****
+**** Part Type 'PRTR5V0U8S_TSSOP' ('PRTR5V0U8S_TSSOP-NXP-GND=GND_SA') ****
+**** Part Type 'RSMD0603_' ('RSMD0603_-00,') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-100,1%') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-10K,1%') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-1K,1%') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-3.3,1%') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-51,1%') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-6.19K,1%') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-75,1%') ****
+**** Part Type 'RSMD0603_1/10W' ('RSMD0603_1/10W-XX,1%') ****
+**** Part Type 'RSMD0805_125MW' ('RSMD0805_125MW-100,1%') ****
+**** Part Type 'RSMD0805_125MW' ('RSMD0805_125MW-12,1%') ****
+**** Part Type '74LVC1G07_SC70' ('SN74LVC1G07DCK-GND=GND_SIGNAL,A') ****
+**** Part Type 'TP_HOLE' ('TP_HOLE-0.8MM') ****
+**** Part Type 'TRANS MOSFET_GSD' ('TRANS MOSFET_GSD-FDV301N,SOT23') ****
+**** Part Type 'USBLC6-2_SOT23' ('USBLC6-2SC6') ****
+**** Part Type 'ZENER_SOD123-CA' ('ZENER_SOD123-CA-BZT52C2V7') ****
+
+END.
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