Fixing typo in process sensitivity list in logic_clocks. Hopefully won't have…

Fixing typo in process sensitivity list in logic_clocks. Hopefully won't have affected function ....

Fixing typo in process sensitivity list in logic_clocks. Hopefully won't have…
Fixing typo in process sensitivity list in logic_clocks. Hopefully won't have affected function ....
def38894 · David Cussans · fd44b29a · def38894
Commit def38894 authored Feb 25, 2020 by David Cussans
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logic_clocks_rtl.vhd AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd +3 -3

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--- a/AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd
+++ b/AIDA_tlu/components/tlu/firmware/hdl/logic_clocks_rtl.vhd
@@ -220,9 +220,9 @@ BEGIN
      end if;
    end process generate_4x_strobe;
-  -- Generate a strobe signal for 160MHz clock
+  -- Generate a strobe signal for 320MHz clock
-    generate_8x_strobe: process (s_clk160_internal, s_clk40)
+    generate_8x_strobe: process (s_clk320_internal, s_clk40)
-    begin  -- process generate_4x_strobe
+    begin  -- process generate_8x_strobe
      if rising_edge(s_clk320_internal) then
        s_clk40_delayed_320 <= s_clk40_delayed_320(s_clk40_delayed_320'left-1 downto 0) & s_clk40;
        strobe_8x_logic_o   <=  s_clk40_delayed_320(s_clk40_delayed_320'left-1) and not s_clk40_delayed_320(s_clk40_delayed_320'left);