Changing read/write of trigger old off register from W to w . New versions of uHAL choke on upper case

Removing TLU manual from Firm(Gate)ware repository. The definitive version is in the 'toplevel' repo: https://ohwr.org/project/fmc-mtlu

Dcussans/update docs

See merge request !5

Dcussans/add ipbus decode tl uaddrmap

See merge request !4

Large number of conflicts reports - but almost all of these seem to have been white-space only

README.md conflict probably not resolved correctly.

Tidying up some files. This seems to have resulted in conflict with master, but I don't know how.

Merging changes back to master. Seems to be in a state where the permissions were wrong. Creating a new branch to merge back to master

Dcussans/8bit fine ts

See merge request !2

generate_bfm_input - text fed into HREAD must be long enough to fill variable ( e.g. HREAD into 32 bit integer needs 8 chars )

dualSERDES_1to_4 - changed delay on delayed IDELAYE2 in order to balance up delays
triggerInputs_newTLU - fixed bug in code to swap between rising and falling edges

TLUaddrmap.xml - added new register for optional invert edge selection.

transactionGenerator_behavioural.vhd - simulation should now finish cleanly, rather than hanging in loop

Inspection "by eye" shows linear correlation between delay of pulse and
fine-grain timestamp.

Use AIDA_tlu/components/tlu/sim/cfg/triggerInputs_newTLU_tb.dep to build with ipbb

This led to some minor changes to logic_clocks. Hopefully making it more robust...

Fixing typo in process sensitivity list in logic_clocks. Hopefully won't have affected function ....

Dcussans/ipbus1v6 update

See merge request !1

Removing unused files.

Should now build against IPBus v1.6

* Incrementing version number ( now v24 )

* Removed unused code and signals.
* Changed way strobes are generated - use 40MHz clock as input. (Should be much more robust than previous mechanism)
Incremented version number to 23