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AIDA-2020 TLU - Gateware
Commit 3ffc883a authored by Alvaro Dosil's avatar Alvaro Dosil
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fix project and i2c bugs

parent 1bdd615f
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Showing with 4 additions and 4 deletions
config/ise14/sp601/coregen.cgp
View file @ 3ffc883a
...@@ -2,8 +2,8 @@ SET busformat = BusFormatAngleBracketNotRipped ...@@ -2,8 +2,8 @@ SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL SET designentry = VHDL
SET device = xc6slx16 SET device = xc6slx16
SET devicefamily = spartan6 SET devicefamily = spartan6
SET flowvendor = Foundation_ISE SET flowvendor = Other
SET package = csg324 SET package = csg324
SET speedgrade = -3 SET speedgrade = -3
SET verilogsim = true SET verilogsim = false
SET vhdlsim = true SET vhdlsim = true
hdl/common/i2c_master_rtl.vhd
View file @ 3ffc883a
...@@ -91,7 +91,7 @@ BEGIN ...@@ -91,7 +91,7 @@ BEGIN
ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0'); ipbus_o.ipb_rdata(31 downto 8) <= ( others => '0');
ipbus_o.ipb_err <= '1'; -- never return an error. ipbus_o.ipb_err <= '0'; -- never return an error.
END ARCHITECTURE rtl; END ARCHITECTURE rtl;
hdl/common/serdesCalibrateFSM_rtl.vhd
View file @ 3ffc883a
...@@ -25,7 +25,7 @@ ...@@ -25,7 +25,7 @@
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--! @todo Implement a periodic calibration sequence\n --! @todo Implement a periodic calibration sequence\n
--! <another thing to do> \n --! <another thing to do> \n
-
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
......
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